Optimizing FIR Filter Mapping on the Morphosys Reconfigurable System
Hassan Diab (1), Issam Damaj (2), Fadi Kurdahi (3) ((1) American, University of Beirut, (2) American University of Beirut, (3) University of, California at Irvine)
TL;DR
This paper introduces optimized FIR filter mappings for the MorphoSys reconfigurable system, improving processing speed through new interconnection schemes and detailed modeling, advancing reconfigurable computing performance.
Contribution
It presents novel optimized FIR filter mappings and a new interconnection scheme for MorphoSys, significantly enhancing processing speed over previous methods.
Findings
Enhanced FIR filter processing speed on MorphoSys
Introduction of a new interconnection scheme
Quantified speedup and mapping advantages
Abstract
This paper proposes an optimized mapping of the FIR filter algorithm that enhances the rate of a reconfigurable computer over a basic mapping previously proposed [1]. It also presents a new interconnection scheme in the reconfigurable part of MorphoSys, a reconfigurable computing system [2]. Reconfigurable computing (RC) is introduced, followed by the MorphoSys RC system. Two optimized FIR mappings are then presented which deliver enhanced speed. A spreadsheet model will detail the modification and the improvement. The speedup achieved is also explained as well as the advantages in the mapping of the application.
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Taxonomy
TopicsEmbedded Systems Design Techniques · VLSI and FPGA Design Techniques · Interconnection Networks and Systems