Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks

TL;DR

This paper demonstrates that Binarized Neural Networks (BNNs) can tolerate high levels of bit errors in resistive RAM (RRAM) hardware, enabling more energy-efficient and robust in-memory neural network implementations.

Contribution

It shows that BNNs can withstand significant bit errors in RRAM devices, and proposes training adaptations to enhance error tolerance, reducing hardware constraints.

Findings

BNNs tolerate up to 10^-4 bit error rate with minimal performance loss.

Training adaptation extends error tolerance to 4x10^-2 bit error rate.

RRAM programming energy can be reduced by a factor of 30.

Abstract

Resistive random access memories (RRAM) are novel nonvolatile memory technologies, which can be embedded at the core of CMOS, and which could be ideal for the in-memory implementation of deep neural networks. A particularly exciting vision is using them for implementing Binarized Neural Networks (BNNs), a class of deep neural networks with a highly reduced memory footprint. The challenge of resistive memory, however, is that they are prone to device variation, which can lead to bit errors. In this work we show that BNNs can tolerate these bit errors to an outstanding level, through simulations of networks on the MNIST and CIFAR10 tasks. If a standard BNN is used, up to 10^-4 bit error rate can be tolerated with little impact on recognition performance on both MNIST and CIFAR10. We then show that by adapting the training procedure to the fact that the BNN will be operated on error-prone hardware, this tolerance can be extended to a bit error rate of 4x10^-2. The requirements for RRAM are therefore a lot less stringent for BNNs than more traditional applications. We show, based on experimental measurements on a RRAM HfO2 technology, that this result can allow reduce RRAM programming energy by a factor 30.

Figures

Tables

Table 1. TABLE I: RRAM programming conditions of Fig.  1 (b-d).

Programming condition	Very strong	Strong	Weak
SET compliance current	$600\mu A$	$55\mu A$	$20\mu A$
RESET voltage	$2.5V$	$2.5V$	$1.5V$
Programming time	$100ns$	$100ns$	$100ns$
Bit error rate		$9.7\times {10}^{-5}$	$3.3\times {10}^{-2}$
Programming energy	$120/150pJ$	$11/14pJ$	$4/5pJ$
(SET/RESET)
Cyclability	$100$	$>10,000$	$>{10}^6$

Equations

$$A=f(\sum _i{W}_i{X}_i),$$

$$A=\underset{i}{\mathrm{POPCOUNT}}(XNOR(W_i,X_i))>T,$$

Full text

I Introduction

Deep neural networks have made fantastic achievements in recent years [1]. Unfortunately, their high energy consumption limits their use in embedded applications [2, 3]. The in- or near-memory hardware implementation of deep neural networks is widely seen as a solution [2, 4, 5, 6], as such implementations could avoid entirely the energy cost of the von Neumann bottleneck. This is especially true with the emergence of novel memory technologies such as resistive random access memory (RRAM), phase change memory or spin torque magnetoresistive memory, which have made tremendous progress in recent years [5]. These technologies provide low-area, fast and non-volatile memory cells, which can be embedded at the core of CMOS.

A challenge of the in-memory implementation of neural networks is the high amount of required memory. Binarized Neural Networks (BNNs) have recently emerged as a possibly ideal solution [7, 8]. These neural networks, where the synaptic weights as well as neuron activation are binary values, can achieve near state-of-the-art performance on image recognition tasks, while using only a fraction of the memory used by conventional neural networks [7, 8]. BNNs are therefore an excellent candidate for hardware implementation where the synaptic weights are stored in RRAMs [5, 9].

Nevertheless, despite their outstanding qualities, emerging memories are prone to device variation [10, 4], which can cause bit errors. In conventional applications, this is solved either by relying on error correcting codes [11], or by programming memory cells with high energy pulses that lead to more reliable programming [10]. In this work, based on the experimental measurements of RRAM cells and system level simulations, we investigate the impact of bit errors on in-memory BNNs. We find that BNNs can exhibit outstanding error tolerance, allowing us to avoid these traditional techniques for dealing with RRAM variability.

After presenting the background of the work (section II):

• •

We show on several tasks that BNNs have a high tolerance to RRAM bit error rate (section III).

• •

We show that this tolerance can be extended to outstanding levels, if the training process of the BNNs takes into account the fact the neural networks is going to be operated on error-prone hardware (section IV).

II Background

Binarized Neural Networks are simplifications of conventional neural networks, where synaptic weights, as well as neuron activation values, assume binary values ($+1$ or $-1$) instead of real values. In these conditions, the equation for neuron activation $A$:

[TABLE]

where $X_{i}$ are the neuron inputs, $W_{i}$ the corresponding synaptic weights and $f$ the non-linear activation function, is considerably simplified

[TABLE]

where $\operatorname*{POPCOUNT}$ is the function that counts the number of $1s$, and $T$ is a learned threshold.

During training, synaptic weights also assume real weights. The binary weights, equal to the sign of the real weight, are used in both the forward and backward passes, while the real weights are updated by the learning rule [7]. Once training is done, the real weights are no longer needed. BNNs are therefore extremely attractive for hardware implementation of inference operation [12] due to their particularly low memory requirement (one bit per synapse), and due to to the fact that resource-hungry real multiplications in eq. (1) are replaced by simple binary XNOR gates in eq. (2). An optimal implementation would be with RRAM [13, 14, 15, 5], as RRAM cells are much more compact than SRAM, and yet non-volatile.

Nevertheless, the challenge of using RRAMs for in-memory computing is their device variation. Fig. 1(a) presents the transmission electron microscopy image of one of our $HfO_{2}$-based RRAM cell, integrated in the backend-of-line of a full CMOS process, on top of the fourth layer of metal, using the same process as [16]. These memory cells can be programmed either in Low Resistance State (LRS, meaning [math]) or High Resistance State (HRS, meaning $1$). Figs. 1(b-d) show programming statistics of kilobit arrays of such memory cells. Table I summarizes the programming conditions used in Figs. 1(b-d), as well as the corresponding RRAM properties: bit error rate, and cyclability (number of times RRAM devices can be programmed before definitive failure).

In Fig. 1(b), the devices are programmed with “very strong” programming conditions (SET compliance current of $600\mu A$, RESET voltage of $2.5V$, programming time $100ns$). These conditions consume high programming energy, and also lead to device aging, causing low endurance: the RRAM devices cannot be programmed more than 100 times. It is seen in Fig. 1(b) that, despite device variation, the distribution of resistance of the LRS and HRS do not overlap at $3\sigma$, leading to a bit error rate lower than $10^{-6}$.

In Fig. 1(c), the devices are programmed with “strong” programming conditions (SET compliance current of $55\mu A$, RESET voltage of $2.5V$, programming time $100ns$). These conditions consume $11$ times less programming energy than the previous ones, and also lead to less device aging. The devices can be programmed more than $10,000$ times. The distribution of resistance of the LRS and HRS do not overlap at $3\sigma$, leading to a bit error rate of $9.7\times 10^{-5}$.

In contrast, in Fig. 1(d), the devices are programmed with “weak” programming conditions (SET compliance current of $20\mu A$, RESET voltage of $1.5V$, programming time $100ns$). These conditions consume thirty times less programming energy than the very strong ones, and have very reduced device aging: they can be programmed millions of times The distribution of resistance of the LRS and HRS do overlap significantly, leading to a high bit error rate of $3.3\times 10^{-2}$.

In applications, this issue of device variability can be dealt with several strategies. Either, we can use very strong programming conditions, causing high energy consumption, larger cell area (as the transistor associated with RRAM cells need to be able to drive high currents), and low endurance. Alternatively, we can rely on error correcting codes [11], causing a very significant overhead to implement decoding circuits [17]. Other strategies such as write termination [18, 19] and adaptive programming [20] can also reduce the impact of device variability, but with the cost of strong area overhead. Now, we look how BNNs can deal with the issue of device variation in a simpler fashion. This is especially important as some strategies proposed to enhance bit error tolerance in synaptic weights such as the reliance on sign-magnitude representation [21] do not apply to BNNs.

III Bit Error Tolerance with Traditional Training Method

To investigate the impact of bit errors due to RRAM device variation in BNNs with synaptic weights stored in RRAMs, we performed multiple BNNs simulations. We first consider a fully connected neural network with two hidden layers of 4096 neurons, a softmax cross entropy loss function and dropout, illustrated in Fig. 2. We trained this neural network on a Nvidia Tesla V100 GPU to perform the traditional MNIST handwritten character recognition task [22] for 1000 epochs. The BNNs were simulated in the python language using the deep learning Tensorflow framework, and an identical training procedure than [7]. Without any bit error, this network achieves a $1.6\%$ error rate on the test dataset.

We then test the neural network again, but introducing random bit errors on the synaptic weights, i.e randomly flipping a fraction $+1$ weights to $-1$, and of $-1$ weights to $+1$. Fig 3(a) shows the test recognition rate on MNIST as the function of the weight bit error rate. We see that bit error rate as high as $10^{-3}$ does not affect the recognition rate. With an error rate of $10^{-2}$ the recognition rate is only slightly reduced from $1.6\%$ to $1.8\%$.

To check that this surprising result is not due to the simplicity of the considered neural network, we also studied a deep convolutional neural network, trained on the much more difficult image recognition CIFAR10 task [23]. The structure of the neural network is presented in Fig. 2. Without bit errors, the test recognition rate is $87.6\%$. All simulations were performed with the Tensorflow deep learning framework [24].

We then perform the simulations including errors. Fig 3(b) shows the test recognition rate on CIFAR10 as the function of the weight bit error rate. Overall, the system is only slightly less robust than in the MNIST case. With an error rate of $10^{-3}$ the recognition rate is reduced from $87.6\%$ to $87.4\%$. With an error rate of $10^{-2}$ it drops to $86.9\%$.

We have seen in section II that in RRAMs, the choice of programming conditions determines the bit error rate. As we only need ensure a bit error rate of $10^{-4}$ to avoid any recognition rate degradation in both MNIST and CIFAR10 tasks, we therefore do not need to use “very strong” programming conditions of Fig. 1 (b) and Table I, but can use the strong conditions. This saves programming energy, cell area and enhance the RRAM endurance, with regards to more conventional applications that would require the reliability of the very strong programming conditions.

IV Adapting the Training Method can Extend the Bit Error Tolerance

We now show that the already high robustness seen in Fig. 3 can be further enhanced if an appropriate training method is used. For this purpose, we retrain the BNNs, but this time including bit errors during the training process, and not only during the testing phase. This way, the training process takes into account the fact that the BNN will be implemented on error-prone RRAM-based systems. The devices subject to errors are chosen independently in training and testing phase: the training phase assumes that the RRAM-based systems will have errors, but does not know which devices will be affected.

More precisely, to train the neural network, we added errors at each iteration. The forward-pass is computed with errors on weights, e.g. $10\%$ are changed from the original weights $W$ to $W_{error}$. During the backward-pass, we reuse the same value of weights $W_{error}$ instead of $W$ to backpropagate through the whole depth of the neural network.

We now check if this training approach leads to more robust neural networks. We performed the adapted training procedure with different error rates during training. Fig. 4 shows the test error rate on the MNIST task, as a function of bit error rate during testing, for several error rates during training. We see that these curves exhibit a maximum when error rate during testing matches the error rate during training: the network indeed finds a structure particularly adapted to the number of bit errors. The recognition rate at this maximum can be very high. For a bit error rate of $0.15$, the recognition rate is $95.9\%$. If errors had not been taken into account during training (dark red line), recognition rate would only be $30.4\%$. This is quite astonishing that we can get the neural network to function so well, with $15\%$ of incorrect weights!

The fact that the recognition rate exhibits a maximum as a function of bit error rate at test time seems counter intuitive. This can however be understood due to the particular properties of BNNs. In these networks, the value of the neurons is binarized, following eq. (2). Having or not having bit errors in the weight $W_{i}$ can shift the mean value of $\operatorname*{POPCOUNT}_{i}(XNOR(W_{i},X_{i}))$. This effect is very strong in the first layer of the neural network, because in MNIST, the input pixels are mostly binary (black or white). Because of this, there can be a situation where when the bit error rate is shifted, the $\operatorname*{POPCOUNT}$ value is always below threshold, or always above threshold $T$. Then, the neuron always has the same value and is useless for classification. For example, for a training bit error rate of $0.3$, and no bit error at test time, $48\%$ of the first layer neurons are in this situation. Whereas only $13\%$ of these neurons are in this situation if the $0.3$ bit error rate is used both during training and testing.

Fig. 5 shows the results of the same study on the CIFAR10 dataset. The results look slightly different than the MNIST case, in that the curves do not exhibit maxima: if the network has been trained with a given bit error rate, having less bit errors during testing is not detrimental.

This can be explained by going back to the principle of BNNs. We observed that when presenting CIFAR10, adding bit errors does not shift significantly the mean values of $\operatorname*{POPCOUNT}_{i}(XNOR(W_{i},X_{i}))$. The difference with MNIST comes from the fact that MNIST images are mostly black and white, whereas the CIFAR10 images feature rich colors. Because of that, the error-induced shift of the mean value of $\operatorname*{POPCOUNT}_{i}(XNOR(W_{i},X_{i}))$ is significant in the case of the first layer of a neural network during MNIST, but much less significant on CIFAR10.

Once again, using this procedure, extremely high amount of bit errors can be tolerated. Bit error rates up to $4\times 10^{-2}$ do not affect the recognition rate. For a bit error rate of $0.15$, the recognition rate is $81.5\%$, instead of $62.2\%$ if errors had not been taken into account during training (navy line).

When using RRAM devices, using the adapted training procedure therefore allows us using directly the “weak” programming conditions of Fig. 1 and Table I, despite its high bit error rate. This can allow us to benefit from its low programming energy, cell area and high endurance of more than one million cycles.

V Conclusion

The in-memory implementation of Binarized Neural Networks (BNNs) with emerging memories such as RRAM is an exciting road for ultralow energy embedded artificial intelligence. A typical challenge of emerging memories is their device variation, which can lead to bit errors. In this work, we have seen that BNNs can tolerate a very high number of bit errors. The BNN is trained in a conventional manner, up to $10^{-4}$ bit error rate on the synaptic weights can be tolerated on both MNIST and CIFAR task. If the BNN, was trained with a specific procedure taking into account the fact that it will be operated on error-prone hardware, up $4\times 10^{-2}$ bit error rate can be tolerated!

These results can have strong impact on emerging memory design and optimization toward neural network implementation. If one accepts to increase device variability and bit error rate, we saw that is is possible to increase the programming energy efficiency by a factor of thirty, decrease the area and increase the endurance of RRAM cells to more than one million cycles. This can significantly enhance their benefits. The results of this paper also highlight the robustness of neural networks, even in the highly digital BNN form, and their adaptability to the constrains of hardware.

Acknowledgment

This work was supported by the European Research Council Starting Grant NANOINFER (715872).