Quantum circuit optimizations for NISQ architectures

TL;DR

This paper presents a circuit synthesis method that optimizes quantum circuits for specific hardware connectivity constraints, demonstrated on major quantum chips and compared across various circuit sparseness levels.

Contribution

The authors develop a new circuit synthesis scheme that respects hardware connectivity, independently of prior similar work, and apply it to real quantum chip architectures.

Findings

Effective circuit transformations for Google's Bristlecone, IBM's Tokyo, and Rigetti's Acorn chips.

Performance varies with circuit sparsity and connectivity constraints.

Independent of similar recent optimization schemes.

Abstract

Currently available quantum computing hardware platforms have limited 2-qubit connectivity among their addressable qubits. In order to run a generic quantum algorithm on such a platform, one has to transform the initial logical quantum circuit describing the algorithm into an equivalent one that obeys the connectivity restrictions. In this work we construct a circuit synthesis scheme that takes as input the qubit connectivity graph and a quantum circuit over the gate set generated by $\{\text{CNOT},R_{Z}\}$ and outputs a circuit that respects the connectivity of the device. As a concrete application, we apply our techniques to Google's Bristlecone 72-qubit quantum chip connectivity, IBM's Tokyo 20-qubit quantum chip connectivity, and Rigetti's Acorn 19-qubit quantum chip connectivity. In addition, we also compare the performance of our scheme as a function of sparseness of randomly generated quantum circuits. Note: Recently, the authors of arXiv:1904.00633 independently presented a similar optimization scheme. Our work is independent of arXiv:1904.00633, being a longer version of the seminar presented by Beatrice Nash at the Dagstuhl Seminar 18381: Quantum Programming Languages, pg. 120, September 2018, Dagstuhl, Germany, slide deck available online at https://materials.dagstuhl.de/files/18/18381/18381.BeatriceNash.Slides.pdf.

Equations

$$f=$$

$$+e(x_3\oplus x_4)+f(x_1\oplus x_2\oplus x_4)$$

$$A=\left(\begin{array}{cccc}0& 1& 0& 0\\ 1& 1& 0& 0\\ 1& 1& 1& 0\\ 1& 1& 0& 1\end{array}\right)$$

$$S=\left(\begin{array}{cc}1& 0\\ 0& i\end{array}\right),T=\left(\begin{array}{cc}1& 0\\ 0& e^{\frac{i\pi }{4}}\end{array}\right)$$

$$S_{k,\text{CNOT}}{S}_{k,H}...S_{1,\text{CNOT}}{S}_{1,H}=C$$

Full text

In this work we construct a circuit synthesis scheme that takes as input the qubit connectivity graph and a quantum circuit over the gate set generated by $\{\text{CNOT},R_{Z}\}$ and outputs a circuit that respects the connectivity of the device. As a concrete application, we apply our techniques to Google’s Bristlecone 72-qubit quantum chip connectivity, IBM’s Tokyo 20-qubit quantum chip connectivity, and Rigetti’s Acorn 19-qubit quantum chip connectivity. In addition, we also compare the performance of our scheme as a function of sparseness of randomly generated quantum circuits, and discuss how to apply our techniques as a subroutine for the more general mapping problem over universal set of gates (Clifford + T).

I Introduction

Near-term quantum devices, such as Noisy Intermediate Scale Quantum Computers (NISQ) Preskill (2018), are limited by sparse qubit connectivity, and many current compilers require that the input circuit takes into account the allowed connectivity of the hardware. In this paper we introduce a circuit synthesis method that takes as input the connectivity of the hardware and the desired transformation that can be produced using gates from the set $\{\text{CNOT},R_{Z}\}$, where $R_{Z}$ denotes an arbitrary rotation about the $Z$ axis of the Block sphere and outputs a circuit that respects the connectivity of the device. Our results show a significant decrease in CNOT count compared to circuit synthesis methods currently in use and allows for efficient circuit synthesis given any arbitrary connectivity. The method we present is a heuristic: finding the exact optimal solution appears intractable Herr et al. (2017).

The concept behind our approach is to take circuit synthesis methods that optimize the CNOT count of the output circuit that perform well under the assumption of full connectivity (Patel et al. (2008) for CNOT circuits and Amy et al. (2014) for CNOT+$R_{Z}$ circuits) and modify them to take into account connectivity constraints. We compare the results to first synthesizing the circuit using the original methods and then accounting for the constraints and found that our approach of considering connectivity constraints and synthesizing the circuit simultaneously produced sizable reductions. These reductions depend on the sparseness of the connectivity and the complexity of the input transformation, as shown in our Results section.

Our method is effective and simple to implement, taking as input the desired transformation (the exact form of which is described in detail in the Section II - Methods) and the graph representing the connectivity of the device and outputting a circuit that respects the allowed connectivity.

The reminder of this paper is organized as follows. In Sec. II we describe our methodology, followed by our results in Sec. III. In Sec. IV we show how to apply our techniques to arbitrary circuits composed of gates from a universal set, discuss the limitations and also compare with state-of-the art methods of general compilers such as the one implemented in Qiskit Abraham et al. (2019). In Sec. V we conclude our manuscript and raise a series of open questions. A fully worked out example that illustrates our methods is depicted in Appendix A.

Note: Recently, the authors of Kissinger and van de Griend independently presented a similar optimization scheme. Our work is independent of Kissinger and van de Griend , being a longer version of the seminar presented by Beatrice Nash at the Dagstuhl Seminar 18381: Quantum Programming Languages, pg. 120, September 2018, Dagstuhl, Germany Mosca et al. (2019), slide deck available online at https://materials.dagstuhl.de/files/18/18381/18381.BeatriceNash.Slides.pdf.

II Methods

In order to perform a CNOT operation between logical qubits mapped to non-adjacent qubits, a sequence of CNOT gates between adjacent qubits is required to indirectly perform the desired operation. If we have linear nearest-neighbor connectivity, then to perform a CNOT between $q_{1}$ and $q_{4}$ can be achieved using the example circuits shown in Fig. 1.

These general templates can be extended to work for any physical qubit connectivity graph. While performing a CNOT operation between any two qubits is possible, it is expensive. The circuit depicted in Fig. 1 (b) requires $4(l-1)$ CNOT gates to perform the operation, where $l$ is the distance between the two qubits. The naïve swap circuit in Fig. 1 (c) requires $1+6(l-1)$ gates. For circuits that dynamically reassign physical and logical qubits, the last two swap gates in Fig. 1 (c) can be removed.

The best current circuit synthesis methods do not account for qubit connectivity when determining the output circuit. CNOT operations in the optimized output circuit must be replaced by templates such as those shown previously to account for the connectivity of the physical device. Given the sparsity of connectivity graphs of near-term quantum devices, this step increases the CNOT count drastically.

II.1 Linear reversible circuit synthesis

The first class of circuits we look at synthesizing are linear reversible circuits consisting of only CNOT gates. In the Clifford + T universal gate set, the only two-qubit gate needed to achieve universal quantum computation is the CNOT gate, and therefore the efficient synthesis of CNOT circuits is useful for optimizing broader classes of circuits given restricted connectivity. Additionally, CNOT gates are far noisier than single qubit gates, and thus minimizing the number of CNOT gates in a circuit is helpful for reducing errors.

Patel, Markov and Hayes give in Patel et al. (2008) an asymptotically optimal algorithm for synthesizing linear reversible circuits assuming full connectivity. The result is a $O(\frac{n^{2}}{\log n})$ size circuit in the worst case, where $n$ is the number of qubits. In Shende et al. (2003) it is proven that, for $n$ qubits, there exists a linear transformation for which the optimal circuit producing that transformation (again, assuming full connectivity) is size $\Omega(\frac{n^{2}}{\log_{2}n})$; hence, the method in Patel et al. (2008) is optimal in the worst case to within a multiplicative constant. However, each single CNOT gate in the output circuit using method Patel et al. (2008) becomes $O(n)$ gates using the template in Fig 1. b to account for connectivity constraints. Thus, the resulting circuit increases to size $O(\frac{n^{3}}{\log n})$ in the worst-case under connectivity constraints. The algorithm we propose in this section improves on this performance, achieving an $O(n^{2})$ worst-case bound on the size of the resulting circuit, regardless of connectivity.

The algorithm in Patel et al. (2008), which is the foundation for that proposed here, takes as input an arbitrary linear transformation represented by a $n\times n$ binary matrix and outputs a circuit that produces the desired transformation.

The initial state of the $n$ qubits is represented by the $n\times n$ identity matrix and each CNOT applied produces a row operation. Specifically, a CNOT with target $i$ and control $j$ multiplies the matrix representation of the circuit by the elementary matrix $A_{i,j}$, which is the matrix with all elements on the diagonal and $(i,j)$ equal to $1$ and all others equal to [math]. This results in the bitwise addition of row $i$ to row $j$. Hence, each row corresponds to the parity of the associated qubit. An example is given in Fig. 2.

The idea behind the process is to reverse engineer a circuit from the matrix representation of the transformation. The algorithm from Patel et al. (2008) is an optimized version of the Gaussian elimination approach to synthesizing the circuit. The steps are as follows:

Reduce the matrix to upper-triangular form. Each row operation corresponds to a CNOT in the output circuit. 2. 2.

Transpose the resulting matrix and repeat, resulting in the identity matrix. 3. 3.

Construct the output circuit from the operations performed in the following order: first, the operations done in 2) with their control/targets flipped and in the same order in which they were performed, and second, the operations done 1), with their control/targets preserved but the order in which they were performed flipped.

The $O(\frac{n^{2}}{\log n})$ upper bound on the number of operations required for this process, as opposed to the $O(n^{2})$ operations required for row reduction via Gaussian elimination, is achieved by partitioning. The matrix is divided into $\frac{n}{\log_{2}n}$ sections of size $\log_{2}n\times n$. Starting with the first section–after placing a $1$ on the diagonal, if necessary–eliminate duplicate sub-rows within that section before performing row reduction normally. Then move on to the next section and do the same for the rows below the first $\log_{2}n$. Continue in this way until the matrix is in upper triangular form, then transpose and repeat.

The algorithm we propose does not make use of the partitioning (although it can be easily altered to do so), because it takes advantage of grouping multiple row operations to perform together. We found that while partitioning works well when physical qubits are fully or very nearly fully connected ($\gtrapprox$ $85$%), for connectivity as sparse as that of near-term devices our algorithm works best without the use of partitioning. Therefore, we do not go into more details of the process; for more information, see Patel et al. (2008).

Now, we give the intuition for the motivation for our method, using an example of a linear transformation on $6$ qubits and their connectivity given in Fig. 3 (see Appendix A for the fully worked-out example). To eliminate the ones in the first column below the first row, the method in Patel et al. (2008) uses row $1$ as the control for each of the operations. Thus, using this example, the sequence of operations for the first column–represented as $(\text{control},\text{target})$–is $(1,3),(1,4),(1,5)$. Under the assumption of full connectivity, this makes no difference. However, with restricted connectivity, each operation requires $4(l-1)$ CNOT gates when using the template in Fig 1.b, where $l>1$ is the length of the shortest path between the two physical qubits. Thus, this sequence of operations requires $4+8+4=16$ CNOT gates. However, if we are to instead perform the row operations $(4,5),(3,4),(1,3)$, the ones below entry $(1,1)$ are still eliminated, and instead of $16$ CNOT gates, only $1+1+4=6$ are required.

Give a connectivity graph and a set of rows, our goal is to find the shortest set of paths through the graph that effectively hits each of the nodes associated with those rows. Then, we want to convert that path into a sequence of operations that effectively eliminates each of the rows, while leaving the rest unchanged.

II.2 Steiner tree problem reduction

This problem reduces to the Steiner tree problem on the connectivity graph $G$ with edge weights of $1$ and the set $S$ equal to the nodes associated with the control and the set of rows to be eliminated. The Steiner tree problem is that of finding the minimum weight tree, $T$, that is a subgraph of $G$ and includes, but is not limited to including, all nodes in $S$. Nodes in $S$ are called terminals, and nodes in $T$ but not in $S$ are known as Steiner nodes. An example is shown in Fig. 4. The reason for this reduction, perhaps not instantly clear, will become so once shown how to transform a tree into a sequence of row operations.

We want to translate this tree, $T_{\{c,S\}}$, where $c$ is the control, into a sequence of operations that effectively eliminates each row in $S\setminus\{c\}$ using only operations between adjacent nodes. $S\setminus\{c\}$ is the set of rows in the linear transformation matrix with ones in their $c$th entry. We now describe in detail the process of converting a tree to a sequence of row operations. Note that the process differs between whether the row operations are performed before or after the transpose step.

In order to convert the tree into a sequence of row operations, we first separate it into a set of edge disjoint sub-trees $\{T_{\{c_{i},S_{i}\}}\}$ with root $c_{i}\epsilon S$ and leaves $S_{i}\setminus\{c_{i}\}\subset S$. The remaining nodes in each sub-tree are Steiner nodes. The first sub-tree, $T_{\{c_{1},S_{1}\}}$, is rooted at $c$. Starting from $c$, grow the sub-tree by traversing $T_{\{c,S\}}$ in breadth first search order. When arriving at a non-leaf terminal $u$, add $u$ to $T_{\{c_{1},S_{1}\}}$ as a leaf and create a new sub-tree containing a copy of $u$ as a root. Once the sub-tree rooted at $c$ is complete, build the sub-trees rooted at its leaves. Continue until all the edges in $T_{\{c,S\}}$ have been added to a sub-tree. The root of each sub-tree will be used as the control to eliminate each of its leaves.

Compute the sequence of row operations as follows. Starting with the last sub-tree constructed, traverse the tree in reverse depth first search order. When traversing an edge $(u,v)$, where $u$ is closer to the root than $v$, add a row operation to the sequence with $u$ as the control and $v$ the target. Once the top of the tree is reached, we have a sequence of operations $R$. Let $R^{\prime}=reverse(R-R[j])$, where $R[j]$ is the last operation in $R$. Now, create $R^{*}$ by removing from $R+R^{\prime}$ those operations with terminals as the targets. $R+R^{\prime}$ applies the row eliminations, while $R^{*}$ undoes those performed on the Steiner nodes, leaving them unchanged. $R+R^{\prime}+R^{*}$ gives the completed sequence of operations for that sub-tree. Add $R+R^{\prime}+R^{*}$ to the overall sequence of operations and move on to the prior sub-tree until all have been traversed.

We give an example in Fig. 5 for the resulting sequence of operations for the tree in Fig. 4 (assuming before the transpose step), using node $1$ as the overall control. Each CNOT in the circuit shown corresponds to a row operation with the same control and target; they are shown this way to help visualize the result. In the resulting circuit, just as in the original algorithm, if these eliminations are performed before the matrix is transposed, their order will be flipped in the resulting circuit. If they occur after, their control/targets will be flipped, but their order will be preserved.

Each edge will be traversed exactly once in this process. Thus, the total number of gates required will be approximately $4*(l-d)$, where $d$ is the number of terminals (excluding the control) and $l$ is the number of edges in the tree. It is clear that for minimum $l$, this is the optimal solution; hence the reduction to the Steiner tree problem.

The minimal Steiner tree problem, however, is NP-hard. There are approximation algorithms that come close to optimal the best being within a factor of $1.39$, given in Byrka et al. (2010), which improved on the previous bound of $1.55$, given in Robins and Zelikovsky (2000). However, their run-time is insufficient for our algorithm, which requires many iterations, two for each row. The algorithm we use, given in Wang (1985), is somewhat of a combination between the better-performing and more efficient approximation algorithms.

Given a set of terminals and a connectivity graph, the algorithm performs breadth-first search outwards from each of the terminals. When the paths collide, the nodes along that path consolidate into a single node and all the edges adjacent to the consolidated nodes are placed adjacent to this new node. The process is restarted with this node as a new terminal. The total time will therefore be $O(d*(|V|+|E|))$, where $d$ is the number of terminals. The resulting Steiner tree is within a factor of $2(1-\frac{1}{l})$ times the size of the optimal tree, where $l$ is the number of leaves in the optimal tree. From many trials, it seems that this approximation is sufficient to see a large reduction in the CNOT count of the output circuit. The choice of Steiner tree approximation algorithm for this purpose depends on the user’s efficiency and performance requirements; a survey is given in Hwang and Richards (1992).

The algorithm thus far works as follows:

Start with column $i=1$. 2. 2.

If entry $(i,i)=0$, find all rows $j$ such that $(j,i)=1$ and $j>i$. Choose $j$ with the shortest path in the connectivity graph to $i$, and use this path to perform a series of allowed row operations that adds row $j$ to row $i$. 3. 3.

Find rows below row $i$ with entry in column $i$ equal to $1$. Create set of terminals $S$ from nodes associated with those rows in addition to node ${i}$. 4. 4.

Find Steiner graph approximation with connectivity graph $G$ and terminals $S$. 5. 5.

Compute row operations using this graph that eliminate those rows with constraints on allowed row operations. Perform those operations and compute resulting matrix. 6. 6.

Repeat steps 2-5 on the next columns, until the matrix is in upper-triangular form. 7. 7.

Transpose the matrix and repeat.

After the matrix is transposed, we must alter step $5$ in the process slightly. Now, say that a row operation is effectively performed between $(i,j)$, with $i$ as the control, and $j$ as the target. If $i>j$, then the lower-triangular form of the matrix is ruined. Thus, we have to alter the algorithm so as to only allow effective row operations with a lower index row as the control and a higher index as the target.

To do this, perform the Steiner tree algorithm as before, except use the smallest node as the control for all of the operations. Fig. 6 shows how to eliminate two rows on the same path, which is never necessary before the transpose step. From Fig. 6 it is clear that the maximum number of additional gates required to ensure this requirement is $4*d$.

Let the output sequence of operations before the transpose step be a list $A$ and after the transpose step be a list $B$. When adding each operation to the output sequence $B$, flip the control and target. The output circuit will be: $B+\textit{reverse}(A)$.

The Steiner tree approximations will always be size $O(n)$. Since the number of operations is $O(4*(\text{size of tree}))$, then the operations required will be $O(n)$. Since there are $O(n)$ trees computed in total throughout the execution of the algorithm ($O(1)$ per column), then the overall number of operations is $O(n^{2})$, regardless of connectivity.

II.3 CNOT + phase circuit synthesis

The other class of circuits we look at synthesizing given connectivity constraints are those consisting of CNOT gates and $Z$-basis rotations of arbitrary angles. Amy, Azimzadeh, and Mosca give in Amy et al. (2014) a heuristic algorithm for the efficient synthesis of CNOT count optimized circuits in this class assuming full connectivity. The results in Amy et al. (2014) show a $23\%$ decrease in the CNOT count on average for a suite of Clifford+T benchmark circuits.

The $\{CNOT,R_{z}\}$ circuit to be synthesized is described by its phase polynomial $f$ and matrix $A$ representing the overall linear transformation on the basis states. $(f,A)$, known as the sum-over-paths form, fully defines the desired unitary transformation applied by the output circuit, $U_{C}$. For a size $n$-qubit circuit:

$U_{C}=\sum_{\mathbf{x}\epsilon\mathbb{F}_{2}^{n}}e^{2\pi if(\mathbf{x})}\ket{A\mathbf{x}}\bra{\mathbf{x}},$

where $\mathbb{F}_{2}^{n}$ is the set of all length $n$ bit strings, and $f(\mathbf{x})$ is given by:

$f(\mathbf{x})=\sum_{\mathbf{y}\epsilon\mathbb{F}_{2}^{n}}\hat{f}(\mathbf{y})(x_{1}y_{1}\oplus x_{2}y_{2}\oplus...\oplus x_{n}y_{n}).$

$f(\mathbf{x})$ is the Fourier expansion of $f$ with Fourier coefficients $\hat{f}(\mathbf{y})$. Let the support of $\hat{f}$, $\text{supp}(\hat{f})$, be the parities with nonzero Fourier coeffiecient. Since the application of a CNOT gate with control $x_{1}$ and target $x_{2}$ maps $\ket{x_{1},x_{2}}$ to $\ket{x_{1},x_{1}\oplus x_{2}}$, the state of each qubit can be mapped to a bit string representing a parity. Each $R_{Z}$ gate is determined by the parity of the state of the qubit on which it is applied at that point in the circuit. The coefficients for each parity $\mathbf{y}\epsilon\mathbb{F}_{2}^{n}$, $\hat{f}(\mathbf{y})$, are given by the sum of the $Z$ rotation angles on that parity. Hence $R_{Z}$ gates acting on the same parity can be combined. For example, the phase polynomial $f$ and basis state transformation $A$ associated with the circuit shown in Fig. 7 is:

[TABLE]

[TABLE]

The method in Amy et al. (2014) first synthesizes a circuit with the input phase polynomial $f$, then uses the method in Patel et al. (2008) to produce the basis state transformation given by input matrix $A$. To do the former, the goal is to compute a minimal parity network. A parity network is a circuit in which every parity in a set $S$ appears. In our case, $S=\text{supp}(\hat{f})$. By applying $R_{Z}(\theta)$, with $\theta=\hat{f}(\mathbf{y})$, to each parity $\mathbf{y}\epsilon S$, the resulting circuit will have the desired phase polynomial. To apply the linear transformation to the basis states given by $A$, first compute the linear transformation $C$ resulting from the parity network. Using the method described previously, compute the circuit the linear transformation $AC^{-1}$ and append it to the end of the existing circuit.

To find the exact minimal parity network, however, is NP-hard; a a heuristic for synthesizing an approximation is given in Amy et al. (2014). The algorithm works as follows:

Represent the set of parities as a matrix $P$, where each column corresponds to a parity and each row to a qubit. For example, $P$ associated with the circuit given in Fig. 7 is

$\begin{pmatrix}1&0&1&1&0\\ 0&1&1&1&0\\ 0&0&1&0&1\\ 0&0&0&1&1\end{pmatrix}$

where the first column corresponds to parity $x_{1}$, the second to parity $x_{2}$, the third to parity $x_{1}\oplus x_{2}\oplus x_{3}$, the fourth to parity $x_{1}\oplus x_{2}\oplus x_{4}$, and the last to parity $x_{3}\oplus x_{4}$. 2. 2.

Find the row $j$ (of those not yet recursed on) such that:

$j=\text{arg max}_{i\epsilon\text{cols}(P)}\text{max}_{x\epsilon\{0,1\}}\{|P_{j,i}=x|\}.$ 3. 3.

Separate $P$ into $P^{0}$, the columns $i$ with $P_{j,i}=0$, and $P^{1}$, those with $P_{j,i}=1$. 4. 4.

Recurse on $P^{0}$. 5. 5.

For $P^{1}$, find row $i\neq j$ such that all elements in row $i$ of $P^{1}$ equal $1$. Add a CNOT with control $i$ and target $j$ to our parity network. Set $P_{i}=P_{i}+P_{j}$. Repeat until no more such rows are found. 6. 6.

Recurse on $P^{1}$.

A detailed example of this process can be found in Amy et al. (2014). Our method performs the same series of steps, except step $5$ is modified as follows:

Compute the approximate Steiner tree of the connectivity graph $G$ with $S$ equal to the set of rows $\{i\}$ such that each element in row $i$ of $P^{1}$ equals $1$. Using row $j$ as the control, eliminate them all together in the same manner described in the previous section.

In this case, whether the control bit has greater index than the target is not relevant.

Each parity in $\text{supp}(\hat{f})$ will appear at least once in this circuit. For each $\mathbf{y}\text{ }\epsilon\text{ supp}(\hat{f})$, apply gate $R_{Z}(\hat{f}(\mathbf{y}))$ to the qubit with incoming parity $\mathbf{y}$. Lastly, append the circuit producing linear transformation $AC^{-1}$, taking into account connectivity constraints, using the algorithm described previously.

III Results

In this section we compare the size of the output circuits generated using the algorithm described in the previous sections to those generated by first synthesizing the circuit using the method in Patel et al. (2008) (for linear reversible circuits) or Amy et al. (2014) (for CNOT + T circuits) without taking into account connectivity constraints, then, once the circuit has been synthesized, using the template given in Fig. 1 (b) to take into account the connectivity. In both cases, after the circuit has been synthesized, we further optimize the size of the resulting circuit by commuting operators and canceling where possible.

We investigate random circuits on 20 qubits with varying connectivity (results depicted in Fig. 8 and Fig. 13), the Google Bristlecone 72 qubit architecture (results depicted in Fig. 9 and Fig. 13), the IBM Tokyo 20 qubit architecture (results depicted in Fig. 13, and the Rigetti’s Acorn 19 qubit architecture (results depicted in Fig. 13.

IV Universal Gate Sets

We briefly discuss extending the applications of the method described in this paper to universal gate sets. Circuits consisting of CNOT and phase gates alone are not sufficient for universal quantum computing. Adding the Hadamard gate, $H=\frac{1}{\sqrt{2}}\begin{pmatrix}1&1\\ 1&-1\end{pmatrix}$, to the $\{\text{CNOT},R_{z}\}$ gate set makes it universal. Without compromising the universality of the set, we restrict to specific $z-$rotation gates:

[TABLE]

and their conjugate transposes. Let $\mathbb{U}$ be the set of circuits composed solely of these gates.

We can apply the methods described here to this more powerful class of circuits as follows. Given a circuit $C$ in $\mathbb{U}$, we can optimize for the number of $H$ gates in the circuit using the ”merge and delete” method abd (2014). Then, partition $C$ into $2*k$ segments $S_{a,b}$, $1\leq a\leq k$, $b\in\{\text{CNOT},H\}$, such that

[TABLE]

and each $S_{i,H}$ contains only $H$ gates while each $S_{i,\text{CNOT}}$ contains only gates from $\{\text{CNOT},S,T,S^{{\dagger}},T^{{\dagger}}\}$. Next, we can apply the methods discussed in previous sections to each of the $S_{i,\text{CNOT}}$ segments in order to account for connectivity constraints. As discussed in the previous section, our method performs better as gate count increases, so, ideally, we want to partition the input circuit so that the $S_{i,\text{CNOT}}$ segments are large.

To do so, we use a simple heuristic technique: first, naively partition the input circuit. Say that the size of $C$, excluding $H$ gates, is $n$. Then, for $i=n$ to $1$, commute gate $v_{i}\in\{\text{CNOT},S,T,S^{{\dagger}},T^{{\dagger}}\}$ forward through the circuit until reaching a gate with which it does not commute. Keep track of the largest segment $S_{i_{\text{max}},\text{CNOT}}$ that $v_{i}$ can belong to. Once reaching the end of the circuit or a non-commuting gate, insert $v_{i}$ into $S_{i_{\text{max}},\text{CNOT}}$. Once $v_{1}$ has been reached, repeat this process but in the opposite direction, from $i=1$ to $n$, this time commuting backwards instead of forwards.

The output circuit could then be further optimized using methods that preserve the allowed two-qubit gates, based on templates, for example, or those that dynamically re-allocate physical and logical qubits Li et al. (2018); Murali et al. (2019); Finigan et al. (2018). Of course, our method works best when the segments consisting of CNOT gates are large (many important circuits, such as quantum Fourier transform, fall under this category, increasingly so as the number of qubits increases Nam et al. (2018)). The results are shown in Figure 14 compared to IBM’s Qiskit transpiler and demonstrate that for input circuits with $\lessapprox 0.05-0.07$ Hadamard to CNOT ratio, this method consistently outperforms the Qiskit compiler, while it does increasingly worse as the ratio grows larger. The input circuits have 1000 gates and do not take into account connectivity. To generate the initial circuit, each gate is chosen from the set $\{\text{CNOT},S,T,S^{{\dagger}},T^{{\dagger}},H\}$ with respective probabilities $\{p_{\text{CNOT}},p_{S},p_{T},p_{S^{{\dagger}}},p_{T^{{\dagger}}},p_{H}\}$. For this experiment, $p_{S}=p_{T}=p_{S^{{\dagger}}}=p_{T^{{\dagger}}}=0.01$, $p_{H}\in[0,0.2]$, and $p_{\text{CNOT}}=1-\sum_{i\in\{S,T,S^{{\dagger}},T^{{\dagger}},H\}}p_{i}$.

V Conclusions and open questions

We constructed a circuit synthesis scheme that takes as input the qubit connectivity graph and a quantum circuit over the gate set generated by $\{\text{CNOT},R_{Z}\}$ and outputs a circuit that respects the connectivity of the device. We applied our techniques to Google’s Bristlecone 72-qubit quantum chip connectivity, IBM’s Tokyo 20-qubit quantum chip connectivity, and Rigetti’s Acorn 19-qubit quantum chip connectivity. We also compared the performance of our methods as a function of sparseness of random quantum circuits of 20 qubits.

Since in practice different CNOT gates can be affected by different amount of noise, an idea for further work would be to weight the edges based on the error rate of the CNOT gate between the respective qubits. Techniques adapted from Amy et al. (2014) could potentially be integrated into the methods given in this paper to produce circuits with lower error rates. In addition, we plan to improve on efficiency and quality of the results produced by our scheme.

We show how the method can be applied to broader classes of circuits comprising of universal set of gates, however our scheme performs (as expected) less optimally than compilers designed specifically for that task, while over-performing the latter for circuits comprising of $\{\text{CNOT},R_{Z}\}$.

Acknowledgements.

We thank Matt Amy for very useful comments and discussions. We acknowledge support from NSERC and CIFAR. IQC is supported in part by the Government of Canada and the Province of Ontario. We also want to thank the anonymous referees for the their very helpful suggestions for improving the quality of this manuscript.