Performance-Efficiency Trade-off of Low-Precision Numerical Formats in Deep Neural Networks

TL;DR

This paper analyzes the trade-offs between different low-precision numerical formats for deep neural network inference, demonstrating that posit formats outperform others at 8-bit or less precision with efficient resource use.

Contribution

The study provides a unified analysis of fixed-point, floating point, and posit formats at ≤8-bit precision in DNN accelerators, highlighting the advantages of posit formats.

Findings

Posit formats outperform other low-precision formats at ≤8-bit.

Posit-based DNN inference achieves competitive resource efficiency.

Trade-offs between efficiency and performance are quantified across five tasks.

Abstract

Deep neural networks (DNNs) have been demonstrated as effective prognostic models across various domains, e.g. natural language processing, computer vision, and genomics. However, modern-day DNNs demand high compute and memory storage for executing any reasonably complex task. To optimize the inference time and alleviate the power consumption of these networks, DNN accelerators with low-precision representations of data and DNN parameters are being actively studied. An interesting research question is in how low-precision networks can be ported to edge-devices with similar performance as high-precision networks. In this work, we employ the fixed-point, floating point, and posit numerical formats at $\leq$8-bit precision within a DNN accelerator, Deep Positron, with exact multiply-and-accumulate (EMAC) units for inference. A unified analysis quantifies the trade-offs between overall network efficiency and performance across five classification tasks. Our results indicate that posits are a natural fit for DNN inference, outperforming at $\leq$8-bit precision, and can be realized with competitive resource requirements relative to those of floating point.

Figures

Tables

Table 1. Table 1 . Deep Positron inference accuracy (Acc.) on the five low-dimensional datasets with 8-bit EMACs. The best results arise when posit has e ​ s ∈ { 0 , 1 , 2 } 𝑒 𝑠 0 1 2 es\in\{0,1,2\} , floating point has w e ∈ { 3 , 4 } subscript 𝑤 𝑒 3 4 w_{e}\in\{3,4\} , and fixed-point has Q ∈ { 4 , 5 } 𝑄 4 5 Q\in\{4,5\} .

				Floating	Fixed-	32-bit
			Posit	Point	Point	Float
Dataset	Inference Size		Acc. ($es$)	Acc. ($w_e$)	Acc. ($Q$)	Acc.
WI Breast Cancer (Street et al., 1993)	190		85.9% (2)	77.4% (4)	57.8% (5)	90.1%
Iris (Fisher, 1936)	50		98.0% (1)	96.0% (3)	92.0% (4)	98.0%
Mushroom (Schlimmer, 1987)	2,708		96.4% (1)	96.4% (4)	95.9% (5)	96.8%
MNIST (LeCun, 1998)	10,000		98.5% (1)	98.4% (4)	98.3% (5)	98.5%
Fashion MNIST (Xiao et al., 2017)	10,000		89.6% (1)	89.6% (4)	89.2% (4)	89.5%

Table 2. Table 2 . Comparison of posit arithmetic hardware implementations.

Design	(Jaiswal and So, 2018b)	(Chaurasiya et al., 2018)	(Podobas and Matsuoka, 2018)	(Chen et al., 2018)	(Lehóczky et al., 2018)	(Johnson, 2018)	This Work
Device	Virtex-6 FPGA/ASIC	Zynq-7000 SoC/ASIC	Stratix V GX	Virtex7 VX690 & Ultrascale	Artix-7 FPGA	ASIC	Virtex-7 (xc7vx485t-2ffg1761c)
			5SGXA7 FPGA	Plus VU3P FPGAs			FPGA
Task	-	FIR Filter	-	-	-	Image Classification	Image Classification
Dataset	-	-	-	-	-	ImageNet	WI Breast Cancer, Iris, Mush-
							room, MNIST, Fashion MNIST
Bit-precision	All	All	All	32	All	All, emphasized on 8	All, emphasized on $[5,8]$
Operations	Mul,Add/Sub	Mul,Add/Sub	Mul,Add/Sub	Quire	Quire	Quire	Quire
Programming Language	Verilog	Verilog	C++ /OpenCL	Verilog	C#	OpenCl	VHDL
Technology Node	40 nm / 90 nm	28 nm / 90 nm	28 nm	28 nm / 20 nm	28 nm	28 nm	28 nm

Equations

$$\underset{n\text{leavevmode}\text{Bits}}{\underbrace{\stackrel{\text{Sign}}{\overbrace{s}}\stackrel{\text{Regime}}{\overbrace{r\text{leavevmode}r\text{leavevmode}...\text{leavevmode}r\text{leavevmode}\bar{r}\text{leavevmode}}}\stackrel{\text{Exponent, if any}}{\overbrace{e_1\text{leavevmode}{e}_2\text{leavevmode}{e}_3\text{leavevmode}...\text{leavevmode}{e}_{es}\text{leavevmode}}}\stackrel{\text{Mantissa, if any}}{\overbrace{f_1\text{leavevmode}{f}_2\text{leavevmode}{f}_3\text{leavevmode}...}}}}$$

$$(-1{)}^s\times {\left(2^{2^{es}}\right)}^k\times 2^e\times 1.f$$

$$w_a=\lceil {\log }_2(k)\rceil +2\times \lceil {\log }_2\left(\frac{max}{min}\right)\rceil +2$$

$$max$$

$$min$$

$$bias$$

$$ex{p}_{max}$$

$$max$$

$$min$$

$$useed$$

$$max$$

$$min$$

$$\text{MSE}(X,X_{quant})=\frac{1}{n}\sum _i^n{\left(X-X_{quant}\right)}^2$$

Full text

DNN accelerators, posit numerical format, deep neural networks, machine learning, floating point, tapered precision, low-precision

††journalyear: 2019††copyright: acmlicensed††conference: Conference for Next Generation Arithmetic 2019; March 13–14, 2019; Singapore, Singapore††booktitle: Conference for Next Generation Arithmetic 2019 (CoNGA’19), March 13–14, 2019, Singapore, Singapore††price: 15.00††doi: 10.1145/3316279.3316282††isbn: 978-1-4503-7139-1/19/03††ccs: Hardware Hardware accelerators††ccs: Computing methodologies Neural networks

1. Introduction

The deep neural network (DNN) is a popular learning paradigm that can generalize to tasks from disparate domains while achieving state-of-the-art performance. However, these networks are computationally heavyweight with regard to both compute and memory resources. For example, an outrageously large neural network with 32-bit floating point, such as an LSTM with a mixture of experts (Shazeer et al., 2017), approximately requires 137 billion parameters. To manage the training and batch inference of these networks, hardware accelerators are employed, such as Google’s Tensor, Processing Unit to decrease latency and increase throughput, embedded and/or reconfigurable devices to mitigate power bottlenecks, or targeted ASICs to optimize the overall performance. A predominant factor contributing to the computational cost is the large footprint of primitives, known as multiply-and-accumulate (MAC) operations, which perform weighted summations of the neuronal inputs. Techniques such as sparsity and low-precision representation (Han et al., 2016; Wu et al., 2018; Chung et al., 2018; Colangelo et al., 2018) have been extensively studied to reduce the cost associated with MACs. For example, substituting 8-bit fixed-point for 32-bit fixed-point when performing inference on CIFAR-10 with AlexNet reduces the energy consumption 6$\times$ (Hashemi et al., 2017). These techniques become a necessity when deploying DNNs on end-devices, such as AI on the edge or IoT devices.

Of the methods used to mitigate these constraints, low-precision techniques have shown the most promise. For example, linear and nonlinear quantization have been able to match 32-bit floating point performance with 8-bit fixed-point and 8-bit floating point accelerators (Jouppi et al., 2017; Reagen et al., 2016; Chung et al., 2018). However, quantizing to an ultra-low bit precision, i.e. $\leq$8-bits, can necessitate an increase in computational complexity. For example, a DNN has to be retrained or the number of hyperparameters significantly increased (Mishra and Marr, 2018) to maintain performance. A more lightweight solution is to perform DNN training and inference at a low-precision numerical format (fixed-point, floating point, or posit (Gysel, 2016)) instead of quantizing a trained network (e.g. with 32-bit floating point). Previous studies have compared DNN inference with low-precision (e.g. 8-bit) to high-precision floating point (e.g. 32-bit) (Hashemi et al., 2017). However, these works compare numerical formats with disparate bit-widths and thereby do not fairly provide a comprehensive, holistic study of the network efficiency.

The recently proposed posit numerical format offers wider dynamic range, better accuracy, and improved closure over IEEE-754 floating point (Gustafson and Yonemoto, 2017). Fig. 1 shows intuitively that a natural posit distribution (e.g. 8-bit posit, $es=0$) may be an optimal fit for representing DNN parameters (e.g. of ConvNet). In this work, we investigate the effectiveness of ultra-low precision posits for DNN inference. The designs of several multiply-and-accumulate units for the posit, fixed-point, and floating point formats at low-precision are analyzed for resource utilization, latency, power consumption, and energy-delay-product. We carry out various classification tasks and compare the trade-offs between accuracy degradation and hardware efficacy. Our results indicate that posits outperform at ultra-low precision and can be realized at a similar cost to floating point in DNN accelerators.

2. Related Work

Since the late 1980s, low-precision fixed-point and floating point computation have been studied (Iwata et al., 1989; Hammerstrom, 1990). In recent years, research attention has increased towards deep learning applications. Multiple groups have demonstrated that 16-bit fixed-point DNNs can perform inference with trivial degradation in performance (Courbariaux et al., 2014; Bengio, 2013). However, most of these works study DNN inference at varying bit-precision. There is a need for a more fair comparison between different number formats of corresponding bit-width paired with FPGA soft cores. For instance, Hashemi et al. analyze 32-bit fixed-point and 32-bit floating point DNN inference on three DNN architectures (LeNet, ConvNet, and AlexNet) and show that fixed-point reduces the energy consumption by $\sim$12% while suffering a mere 0–1% accuracy drop (Hashemi et al., 2017). Recently, Chung et al. proposed a DNN accelerator (Brainwave) that increases inference throughput within a Stratix-10 FPGA by 3$\times$ by substituting 8-bit ms-fp8, a novel spatial floating point format, in place of 8-bit fixed-point (Chung et al., 2018).

Several groups have previously studied the usage of the posit format in DNNs. Langroudi et al. study the efficacy of posit representations of DNN parameters and activations (Langroudi et al., 2018). The work demonstrates that DNN inference using 7-bit posits endures $<$1% accuracy degradation on ImageNet classification using AlexNet and that posits have a 30% less ravenous memory footprint than fixed-point for multiple DNNs while maintaining a $<$1% drop in accuracy. Cococcioni et al. review the effectiveness of posits for autonomous driving functions (Cococcioni et al., 2018). A discussion of a posit processing unit as an alternative to a floating point processing unit develops into an argument for posits as they exhibit a better trade-off between accuracy and implementation complexity. Most recently, J. Johnson proposed a log float format which couples posits with a logarithmic EMAC operation referred to as exact log-linear multiply-add (ELMA) (Johnson, 2018). Use of the novel format within ResNet-50 achieves $<$1% accuracy deterioration for ImageNet classification, and the ELMA shows much lower power consumption than the IEEE-754 floating point.

In this work, we demonstrate that posit arithmetic at ultra-low bit-width is an innate fit for DNN inference. The EMAC-equipped, parameterized Deep Positron architecture is mounted on an FPGA soft processor and compares assiduously the fixed-point, floating point, and posit formats at same bit-width.

3. Background

3.1. Deep Neural Networks

The DNN is a connectionist, predictive model used commonly for classification and regression. These networks learn a nonlinear input-to-output mapping in either a supervised, unsupervised, or semi-supervised manner. Before being able to perform inference, a DNN is trained to minimize a cost function and update parameters, called weights and biases, using backpropagation. Customarily, either 16-bit or 32-bit floating point arithmetic is used for DNN inference. However, 32-bit IEEE-754 floating point representation maintains a massive dynamic range of over 80 decades, which is beyond the range required for DNNs. Thus, this design of numerical distribution yields low information-per-bit based on Shannon maximum entropy (Shannon, 1948). 16-bit floating point, often present in NVIDIA accelerators, unveils the format’s limitations: nontrivial exception cases, underflow and overflow to $\pm$infinity or zero, and redundant NaN and zero representations. Posit arithmetic offers an elegant solution to these limitations at generic bit-width.

3.2. Posit Numerical Format

The posit numerical format, a Type III unum, was proposed to improve upon the deficiencies of the IEEE-754 floating point format and to address complaints about Type I and II unums (Gustafson and Yonemoto, 2017; Tichy, 2016). The posit format offers better dynamic range, accuracy, and program reproducibility than IEEE floating point. A posit number comprises $n$ bits and $es$ exponent bits, which controls the dynamic range. The primary divergence posit takes from floating point is the introduction of a signed, run-length encoded regime bit-field. The longer this field is, a posit number has lower precision but larger magnitude, and vice versa for shorter run-lengths. Two posit bit-strings are reserved: $\tt{00}...\tt{0}$ for zero and $\tt{10}...\tt{0}$ for “Not a Real,” which can denote infinity, division by zero, etc.. The following shows the interpretation of a binary posit bit-string.

[TABLE]

The numerical value a posit represents is then given by (1)

[TABLE]

where $k$ is the regime, $e$ is the unsigned exponent ($es>0$), and $f$ is the value of the fraction bits. If a posit number is negative, the 2’s complement is taken before decoding. We recommend reviewing (Gustafson and Yonemoto, 2017) for a more thorough introduction and intuition to the posit format.

4. Methodology

We build off of (Carmichael et al., 2019), using the proposed Deep Positron architecture. The framework is parameterized by bit-width, numerical type, and DNN hyperparameters, so networks of arbitrary width and depth can be constructed for the fixed-point, floating point, and posit formats. The following sections further describe the EMAC operation and detail the EMAC algorithms for each numerical format.

4.1. Exact Multiply-and-Accumulate (EMAC)

The multiply-and-accumulate (MAC) operation is ubiquitous within DNNs – each neuron computes a weighted sum of its inputs. In most implementations, this operation is usually inexact, meaning rounding or truncation results in accumulation of error. The EMAC mitigates this issue by implementing a variant of the Kulisch accumulator (Kulisch, 2013) and delaying error until every product of each layer has been accumulated. This minimization of local error becomes substantial at low-precision. In each EMAC module, a wide register accumulates fixed-point values and rounds in a deferred stage. For $k$ multiplications, the accumulator width is computed using (2)

[TABLE]

where $max$ and $min$ are the maximum and minimum value magnitudes for a given numerical system, respectively. Each EMAC is pipelined into three stages: multiplication, accumulation, and rounding. A fourth stage, implementing the trivial activation function, $\textup{ReLU}(x)=\textup{max}(x,0)$, is present for hidden layer neurons. For further introduction to EMACs and the exact dot product, we recommend reviewing (Kulisch, 2013; Carmichael et al., 2019).

4.2. Fixed-Point EMAC

We parameterize the fixed-point EMAC as $n$, the bit-width, and $Q$, the number of fractional bits, where $n>Q$. Fig. 2 shows the block diagram design of the EMAC with signal bit-widths indicated. The functionality of the unit is described by Algorithm 1. The general characteristics of a fixed-point number are given by the following.

[TABLE]

4.3. Floating Point EMAC

The floating point EMAC is parameterized by $w_{e}$, the number of exponent bits, and $w_{f}$, the number of fractional bits. As all inputs and intermediate values in Deep Positron are real-valued, we do not consider “Not a Number” (NaN) or “$\pm$ Infinity” in this implementation. Fig. 3 shows the floating point EMAC block diagram with labeled bit-widths of signals. A leading-zeros-detector (LZD) is used in converting from fixed-point back to floating point. The EMAC functionality is expressed in Algorithm 4.3, and the relevant characteristics of the floating point format are computed as follows.

[TABLE]

Algorithm 2 Floating point EMAC operation.

1:procedure FloatEMAC(${\tt{s_{wgt}}},{\tt{m_{wgt}}},{\tt{e_{wgt}}},{\tt{s_{act}}},{\tt{m_{act}}},{\tt{e_{act}}}$) Subnormal Detection

2:     ${\tt zero_{wgt}}\leftarrow|{\tt e_{wgt}}$

3:     ${\tt zero_{act}}\leftarrow|{\tt e_{act}}$

4:     {\tt ms_{wgt}}\leftarrow{\sim}{\tt zero_{wgt}}\&{\tt m_{wgt}}$$\triangleright Add hidden bit to mantissa

5:     {\tt ms_{act}}\leftarrow{\sim}{\tt zero_{act}}\&{\tt m_{act}}$$\triangleright Add hidden bit to mantissa  Multiplication

6:     ${\tt{s_{p}}}\leftarrow{\tt{s_{wgt}}}\oplus{\tt{s_{act}}}$

7:     ${\tt{m_{p}}}\leftarrow{\tt{ms_{wgt}}}\times{\tt{ms_{act}}}$

8:     ${\tt{e_{p}}}\leftarrow{\tt{e_{wgt}}}+{\tt{e_{act}}}+{\tt zero_{wgt}}+{\tt zero_{act}}+1$  Conversion to Fixed-Point

9:     {\tt m_{fx}}\leftarrow{\tt s_{p}}\leavevmode\nobreak\ ?\leavevmode\nobreak\ \scalebox{0.75}[1.0]{-}{}{\tt m_{p}}:{\tt m_{p}}

10:     {\tt m_{fx}}\leftarrow{\tt m_{fx}}\ll({\tt e_{p}}-3)$$\triangleright Min exponent is 3  Accumulate

11:     ${\tt sum}\leftarrow{\tt m_{fx}}+{\tt sum}$  Convert Back to Floating Point111Note that during the conversion back to floating point overflow handling is omitted for simplicity.

12:     ${\tt s_{r}}\leftarrow{\tt sum}[{\tt MSB}]$

13:     {\tt mag}\leftarrow{\tt s_{r}}\leavevmode\nobreak\ ?\leavevmode\nobreak\ \scalebox{0.75}[1.0]{-}{}{\tt sum}:{\tt sum}

14:     {\tt ovf}\leftarrow{\sim}|{\tt sum}[{\tt MSB}:exp_{max}\scalebox{0.75}[1.0]{-}3]

15:     ${\tt zc}\leftarrow\textup{LZD}({\tt mag})$

16:     {\tt m_{r}},{\tt guard},{\tt sticky}\leftarrow{\tt mag}[{\tt MSB}\scalebox{0.75}[1.0]{-}{}{\tt zc}:{\tt MSB}\scalebox{0.75}[1.0]{-}{}{\tt zc}\scalebox{0.75}[1.0]{-}{}w_{f}\scalebox{0.75}[1.0]{-}{}2]

17:     {\tt e_{r}}\leftarrow exp_{max}\scalebox{0.75}[1.0]{-}{}{\tt zc}$$\triangleright Zeros count is the biased exponent

18:     ${\tt lsb}\leftarrow{\tt m_{r}}[0]$

19:     {\tt rc}\leftarrow{\tt guard}\leavevmode\nobreak\ \&\leavevmode\nobreak\ ({\tt lsb}|{\tt sticky})$$\triangleright Round check

20:     ${\tt m_{r}}\leftarrow{\tt m_{r}}+{\tt rc}$

21:     ${\tt result}\leftarrow\{{\tt s_{r}},{\tt e_{r}},{\tt m_{r}}\}$

22:end procedure

4.4. Posit EMAC

The posit EMAC, shown in Fig. 4, is parameterized by $n$, the bit-width, and $es$, the number of exponential bits. In this implementation, we do not consider “Not a Real” as all DNN parameters and data are real-valued and posits do not overflow to infinity. Algorithm 3 describes the data extraction process for each EMAC input, which is more involved per the dynamic length regime. The EMAC employs this process as outlined by Algorithm 4.4. The relevant attributes of a given posit format are calculated using the following,

[TABLE]

where $useed$ can be thought of as the scale factor base, as shown in (1).

Algorithm 4 Posit EMAC operation for $n$-bit inputs each with $es$ exponent bits

1:procedure PositEMAC($\tt{weight,activation}$)

2:     ${\tt{sign_{w}}},{\tt{reg_{w}}},{\tt{exp_{w}}},{\tt{frac_{w}}}\leftarrow\text{{\normalsize\centering Decode\@add@centering}}({\tt{weight}})$

3:     ${\tt{sign_{a}}},{\tt{reg_{a}}},{\tt{exp_{a}}},{\tt{frac_{a}}}\leftarrow\text{{\normalsize\centering Decode\@add@centering}}({\tt{activation}})$

4:     {\tt{sf_{w}}}\leftarrow\{{\tt{reg_{w}}},{\tt{exp_{w}}}\}$$\triangleright Gather scale factors

5:     ${\tt{sf_{a}}}\leftarrow\{{\tt{reg_{a}}},{\tt{exp_{a}}}\}$  Multiplication

6:     ${\tt{sign_{mult}}}\leftarrow{\tt{sign_{w}}}\oplus{\tt{sign_{a}}}$

7:     ${\tt{frac_{mult}}}\leftarrow{\tt{frac_{w}}}\times{\tt{frac_{a}}}$

8:     {\tt{ovf_{mult}}}\leftarrow{\tt{frac_{mult}}}[{\tt{MSB}}]$$\triangleright Adjust for overflow

9:     ${\tt{normfrac_{mult}}}\leftarrow{\tt{frac_{mult}}}\gg{\tt{ovf_{mult}}}$

10:     ${\tt{sf_{mult}}}\leftarrow{\tt{sf_{w}}}+{\tt{sf_{a}}}+{\tt{ovf_{mult}}}$  Accumulation

11:     {\tt{fracs_{mult}}}\leftarrow{\tt{sign_{mult}}}\leavevmode\nobreak\ ?\leavevmode\nobreak\ {\scalebox{0.75}[1.0]{-}\tt{frac_{mult}}}:{\tt{frac_{mult}}}

12:     {\tt{sf_{biased}}}\leftarrow{\tt{sf_{mult}}}+bias$$\triangleright Bias the scale factor

13:     {\tt{fracs_{fixed}}}\leftarrow{\tt{fracs_{mult}}}\ll{\tt{sf_{biased}}}$$\triangleright Shift to fixed

14:     {\tt{sum_{quire}}}\leftarrow{\tt{fracs_{fixed}}}+{\tt{sum_{quire}}}$$\triangleright Accumulate  Fraction & SF Extraction

15:     ${\tt{sign_{quire}}}\leftarrow{\tt{sum_{quire}}}[{\tt{MSB}}]$

16:     {\tt{mag_{quire}}}\leftarrow{\tt{sign_{quire}}}\leavevmode\nobreak\ ?\leavevmode\nobreak\ {\scalebox{0.75}[1.0]{-}\tt{sum_{quire}}}:{\tt{sum_{quire}}}

17:     ${\tt{zc}}\leftarrow\textup{LZD}({\tt{mag_{quire}}})$

18:     {\tt{frac_{quire}}}\leftarrow{\tt{mag_{quire}}}[2{\times}(n\scalebox{0.75}[1.0]{-}2\scalebox{0.75}[1.0]{-}es)\scalebox{0.75}[1.0]{-}1{+}{\tt{zc}}:{\tt{zc}}]

19:     {\tt{sf_{quire}}}\leftarrow{\tt{zc}}\scalebox{0.75}[1.0]{-}bias  Convergent Rounding & Encoding

20:     ${\tt{nzero}}\leftarrow|{\tt{frac_{quire}}}$

21:     ${\tt{sign_{sf}}}\leftarrow{\tt{sf_{quire}}}[{\tt{MSB}}]$

22:     {\tt{exp}}\leftarrow{\tt{sf_{quire}}}[es\scalebox{0.75}[1.0]{-}1:0]$$\triangleright Unpack scale factor

23:     {\tt{reg_{tmp}}}\leftarrow{\tt{sf_{quire}}}[{\tt{MSB}}\scalebox{0.75}[1.0]{-}1:es]

24:     {\tt{reg}}\leftarrow{\tt{sign_{sf}}}\leavevmode\nobreak\ ?\leavevmode\nobreak\ \scalebox{0.75}[1.0]{-}{\tt{reg_{tmp}}}:{\tt{reg_{tmp}}}

25:     {\tt{ovf_{reg}}}\leftarrow{\tt{reg}}[{\tt{MSB}}]$$\triangleright Check for overflow

26:     {\tt{reg_{f}}}\leftarrow{\tt{ovf_{reg}}}\leavevmode\nobreak\ ?\leavevmode\nobreak\ \{\{\lceil\log_{2}(n)\rceil\scalebox{0.75}[1.0]{-}2\{{\tt{1}}\}\}),{\tt{0}}\}:{\tt{reg}}

27:     ${\tt{exp_{f}}}\leftarrow({\tt{ovf_{reg}}}|{\sim}{\tt{nzero}}|{(\tt{\&{\tt{reg_{f}}}}}))\leavevmode\nobreak\ ?\leavevmode\nobreak\ \{es\{{\tt{0}}\}\}:{\tt{exp}}$

28:     {\tt{tmp1}}\leftarrow\{{\tt{nzero}},{\tt{0}},{\tt{exp_{f}}},{\tt{frac_{quire}}}[{\tt{MSB}}\scalebox{0.75}[1.0]{-}1:0],\{n\scalebox{0.75}[1.0]{-}1\{{\tt{0}}\}\}\}

29:     {\tt{tmp2}}\leftarrow\{{\tt{0}},{\tt{nzero}},{\tt{exp_{f}}},{\tt{frac_{quire}}}[{\tt{MSB}}\scalebox{0.75}[1.0]{-}1:0],\{n\scalebox{0.75}[1.0]{-}1\{{\tt{0}}\}\}\}

30:     ${\tt{ovf_{regf}}}\leftarrow\&{\tt{reg_{f}}}$

31:     if ${\tt{ovf_{regf}}}$ then

32:         ${\tt{shift_{neg}}}\leftarrow{\tt{reg_{f}}}-2$

33:         ${\tt{shift_{pos}}}\leftarrow{\tt{reg_{f}}}-1$

34:     else

35:         ${\tt{shift_{neg}}}\leftarrow{\tt{reg_{f}}}-1$

36:         ${\tt{shift_{pos}}}\leftarrow{\tt{reg_{f}}}$

37:     end if

38:     ${\tt{tmp}}\leftarrow{\tt{sign_{sf}}}\leavevmode\nobreak\ ?\leavevmode\nobreak\ {\tt{tmp2}}\gg{\tt{shift_{neg}}}:{\tt{tmp1}}\gg{\tt{shift_{pos}}}$

39:     {\tt{lsb}},{\tt{guard}}\leftarrow{\tt{tmp}}[{\tt{MSB}}\scalebox{0.75}[1.0]{-}(n\scalebox{0.75}[1.0]{-}2):{\tt{MSB}}\scalebox{0.75}[1.0]{-}(n\scalebox{0.75}[1.0]{-}1)]

40:     ${\tt{round}}\leftarrow{\sim}({\tt{ovf_{reg}}}|{\tt{ovf_{regf}}})\leavevmode\nobreak\ ?$ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ \leavevmode\nobreak\ (\leavevmode\nobreak\ {\tt{guard}}\leavevmode\nobreak\ \&\leavevmode\nobreak\ ({\tt{lsb}}\leavevmode\nobreak\ |\leavevmode\nobreak\ (|{\tt{tmp}}[{\tt{MSB}}\scalebox{0.75}[1.0]{-}n:0]))\leavevmode\nobreak\ ):{\tt{0}}

41:     {\tt{result_{tmp}}}\leftarrow{\tt{tmp}}[{\tt{MSB}}:{\tt{MSB}}\scalebox{0.75}[1.0]{-}n{+}1]{+}{\tt{round}}

42:     {\tt{result}}\leftarrow{\tt{sign_{quire}}}\leavevmode\nobreak\ ?\leavevmode\nobreak\ \scalebox{0.75}[1.0]{-}{\tt{result_{tmp}}}:{\tt{result_{tmp}}}

43:     return ${\tt{result}}$

44:end procedure

5. Experimental Results

In all experiments, we synthesize the EMACs onto a Virtex-7 FPGA (xc7vx485t-2ffg1761c) using Vivado 2017.2. and expand upon the results from (Carmichael et al., 2019). With regard to energy and latency, the posit EMAC is competitive with the floating point EMAC. While using more resources for the same bit-precision, posits offer a wider dynamic range at fewer bits while maintaining a faster maximum operational frequency. Moreover, the energy-delay-product of the floating point and posit EMACs are comparable. The fixed-point EMAC, obviously, is uncontested with its resource utilization and latency; its lack of an exponential parameter results in a far more slender accumulation register. However, fixed-point offers poor dynamic range compared with the other formats at the same bit-precision.

The quantization error of a tensor $X$ is computed as the mean-squared-error as shown in (3).

[TABLE]

Fig. 3 shows a layer-wise heatmap of quantization error between formats for the MNIST and Fashion MNIST classification tasks. It is clear that posits suffer the least consequences from quantization, which is especially noticeable at $\leq$5-bit precision.

We evaluate the inference accuracy of several feedforward three- or four-layer neural networks, instantiated on the Deep Positron accelerator, on five datasets. The baseline results are taken from networks trained and evaluated using standard IEEE-754 floating point at 32-bit precision. The inputs and weights of the trained networks are quantized from the 32-bit floating point format to the desired numerical format (either $[5,8]$-bit posit, $[5,8]$-bit floating point, or $[5,8]$-bit fixed-point) via round-to-nearest with ties to even. The best performance is selected among $[5,8]$-bit formats with a sweep of the $es$, $w_{e}$, and $Q$ parameters for the posit, floating point, and fixed-point formats, respectively. Across all tasks, posit either outperforms or matches the performance of fixed-point and floating point, as shown in Table 1. In some cases, an 8-bit posit matches the performance of the 32-bit floating point baseline. An interesting result is that both posit and floating point at 8-bit precision improve upon the baseline performance for the Fashion MNIST task.

We compare energy, delay, and the energy-delay-product against the average Deep Positron performance across all formats with $[5,8]$ bit-precision. Figs. 6 and 7 depict the average accuracy degradation across the five classification tasks against these metrics for each bit-width. Posit consistently outperforms at a slight cost in power. Fixed-point maintains the lowest delay across all bit-widths, as expected, but offers the worst performance. While the floating point EMAC generally uses less power than the posit EMAC, the posit EMAC enjoys lower latencies across all bit-widths whilst maintaining lower accuracy degradation.

5.1. Exploiting the Posit $es$ Parameter

Experimental results in this paper are evaluated by exploiting the performance of posit numerical formats with $es\in\{0,1,2\}$ across five data sets. As is shown in Fig. 6, the energy-delay-product of the posit EMAC is dependent upon the $es$ parameter. For instance, the energy-delay-product of the posit EMAC with $es=0$, on average, is 3$\times$ and 1.4$\times$ less than the energy-delay-product of the posit EMAC with $es=2$ and $es=1$, respectively. On the other hand, the average performance of DNN inference with $es=1$ for the posit EMAC among the five datasets and $[5,7]$ bit-precision is 2% and 4% percent better than with $es=2$ and $es=0$, respectively. Thus, Deep Positron equipped with the posit ($es=1$) EMAC has a better trade-off between energy-delay-product and accuracy for $[5,7]$ bits. For 8-bit, the results suggest that $es=1$ is a better fit for energy-efficient applications and $es=2$ for accuracy-dependent applications.

5.2. Comparison with Other Posit Hardware Implementations

A summary of previous studies which design posit arithmetic hardware is shown in Table 2. Several groups implement posit basic arithmetic algorithms, such as addition, subtraction, multiplication, and exact-dot-product (Quire) on FPGA for various applications (Jaiswal and So, 2018b, a; Chaurasiya et al., 2018; Chen et al., 2018; Podobas and Matsuoka, 2018; Lehóczky et al., 2018; Johnson, 2018). Kumar et al. provided a hardware generator for posit addition, subtraction, and multiplication and showed reduced latency and area consumption of 32-bit posit addition with $es=3$ over IEEE-754 floating point addition (Jaiswal and So, 2018b, a). However, the comparison is between two different FPGA platforms which diminishes the merit of this comparison. They also ignore several characteristic demands for posit arithmetic, such as round-to-nearest with ties to even or unbiased rounding. To better realize the advantages of posit arithmetic over IEEE-754 floating point with complete posit arithmetic features, Chaurasiya et al. proposed a parameterized posit arithmetic hardware generator (Chaurasiya et al., 2018). They emphasized that resource utilization and energy of the posit arithmetic unit is comparable with IEEE-754 float when the same number of bits are considered for both formats. However, the area consumption of the posit hardware is less than IEEE-745 float at similar precision and dynamic range. To simplify and expedite hardware design, as well as improve the usability of posits on heterogeneous platforms, researchers in (Lehóczky et al., 2018) and (Podobas and Matsuoka, 2018) use high-level languages, such as C# and OpenCL, to generate posit arithmetic hardware for FPGAs.

Most of the previous works do not support the exact-dot-product operation and do not design specialized posit arithmetic for deep learning applications as we presented in this paper. In (Carmichael et al., 2019), a parameterized FPGA-mounted DNN accelerator is constructed which employs exact-dot-product algorithms for the posit, fixed-point, and floating point formats. The paper shows strong preliminary results that posits are a natural fit for low-precision inference. Proceeding this work, J. Johnson proposed an exact log-linear multiply-add arithmetic algorithm for deep learning applications using a posit multiplier in the log domain and a Kulisch adder (Johnson, 2018). The results indicate better performance of 8-bit posit multiply-add over 8-bit fixed-point multiply-add with similar accuracy for the ResNet-50 neural network and ImageNet dataset. However, the paper targets an ASIC platform and convolutional neural network at 8-bit precision whereas we study an FPGA implementation and fully-connected neural network at $[5,8]$ bit-precision.

6. Conclusions

We demonstrate that the recent posit numerical system has a high affinity for deep neural network inference at $\leq$8-bit precision. The proposed posit hardware is shown to be competitive with the floating point counterpart in terms of resource utilization and energy-delay-product. Moreover, the posit EMAC offers a superior maximum operating frequency over that of floating point. With regard to performance degradation, direct quantization to ultra-low precision favors posits heavily, surpassing fixed-point vastly. Moreover, the performance of floating point is either matched or surpassed consistently by posits across multiple datasets. The success of prospective new classes of learning algorithms will be coordinately contingent on the underlying hardware.