# A WCET-aware cache coloring technique for reducing interference in real-time systems

## TL;DR

This paper introduces a WCET-aware cache coloring heuristic to partition shared cache in COTS processors, enhancing predictability for real-time systems by reducing interference and improving worst-case execution time estimates.

## Contribution

A novel WCET-aware heuristic for cache coloring that partitions cache based on task needs, improving predictability in real-time systems using COTS processors.

## Key findings

- Heuristic effectively partitions cache to reduce interference.
- Experiments show improved WCET estimates with the proposed method.
- Results demonstrate enhanced system predictability.

## Abstract

The predictability of a system is the condition to give saferbound on worst case execution timeof real-time tasks which are running on it. Commercial off-the-shelf(COTS) processors are in-creasingly used in embedded systems and contain shared cache memory. This component hasa hard predictable behavior because its state depends of theexecution history of the systems.To increase predictability of COTS component we use cache coloring, a technique widely usedto partition cache memory. Our main contribution is a WCET aware heuristic which parti-tion task according to the needs of each task. Our experiments are made with CPLEX an ILPsolver with random tasks set generated running on preemptive system scheduled with earliestdeadline first(EDF).