# Dynamic Power Management for Neuromorphic Many-Core Systems

## TL;DR

This paper introduces a fast, autonomous dynamic power management system for neuromorphic many-core processors, significantly reducing power consumption while maintaining real-time performance.

## Contribution

It presents a novel fast DVFS technique enabling individual, rapid voltage and frequency scaling of processing elements in neuromorphic systems.

## Key findings

- Power consumption reduced by 75% in tests
- 80% baseline power reduction achieved
- Energy per neuron and synapse computation halved

## Abstract

This work presents a dynamic power management architecture for neuromorphic many core systems such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) technique is presented which allows the processing elements (PE) to change their supply voltage and clock frequency individually and autonomously within less than 100 ns. This is employed by the neuromorphic simulation software flow, which defines the performance level (PL) of the PE based on the actual workload within each simulation cycle. A test chip in 28 nm SLP CMOS technology has been implemented. It includes 4 PEs which can be scaled from 0.7 V to 1.0 V with frequencies from 125 MHz to 500 MHz at three distinct PLs. By measurement of three neuromorphic benchmarks it is shown that the total PE power consumption can be reduced by 75%, with 80% baseline power reduction and a 50% reduction of energy per neuron and synapse computation, all while maintaining temporary peak system performance to achieve biological real-time operation of the system. A numerical model of this power management model is derived which allows DVFS architecture exploration for neuromorphics. The proposed technique is to be used for the second generation SpiNNaker neuromorphic many core system.