# A 68 uW 31 kS/s Fully-Capacitive Noise-Shaping SAR ADC with 102 dB SNDR

## TL;DR

This paper introduces a highly energy-efficient 17-bit SAR ADC with advanced noise-shaping, achieving 102 dB SNDR at 31 kS/s in a compact 0.18 um CMOS chip, suitable for low-power high-resolution applications.

## Contribution

It presents a novel fully-capacitive noise-shaping topology and background calibration to significantly enhance dynamic range and reduce oversampling requirements.

## Key findings

- Achieves 102 dB SNDR at 31 kS/s.
- Consumes only 68 uW power.
- Demonstrates 183 dB FoMS in simulation.

## Abstract

This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10x compared to prior-art. A 0.18 um CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoMS of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 uW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm^2 area requirement.