Graph Processing on FPGAs: Taxonomy, Survey, Challenges

TL;DR

This paper provides a comprehensive survey and taxonomy of graph processing on FPGAs, highlighting current methods, challenges, and future directions in energy-efficient graph computation hardware.

Contribution

It is the first survey to categorize and analyze existing FPGA-based graph processing schemes, offering insights into key ideas and research challenges.

Findings

Various FPGA-based graph algorithms exist with different approaches.

Graph processing on FPGAs faces unique challenges due to data irregularity.

Future research should address scalability and power efficiency issues.

Abstract

Graph processing has become an important part of various areas, such as machine learning, computational sciences, medical applications, social network analysis, and many others. Various graphs, for example web or social networks, may contain up to trillions of edges. The sheer size of such datasets, combined with the irregular nature of graph processing, poses unique challenges for the runtime and the consumed power. Field Programmable Gate Arrays (FPGAs) can be an energy-efficient solution to deliver specialized hardware for graph processing. This is reflected by the recent interest in developing various graph algorithms and graph processing frameworks on FPGAs. To facilitate understanding of this emerging domain, we present the first survey and taxonomy on graph computations on FPGAs. Our survey describes and categorizes existing schemes and explains key ideas. Finally, we discuss research and engineering challenges to outline the future of graph computations on FPGAs.