Cryogenic characterization of 28nm FD-SOI ring oscillators with energy efficiency optimization

TL;DR

This paper presents a detailed cryogenic electrical characterization of 28nm FD-SOI ring oscillators, demonstrating energy efficiency improvements at low temperatures through threshold voltage compensation and optimized supply voltages.

Contribution

It introduces a method for threshold voltage compensation via forward body-biasing to enhance energy efficiency of FD-SOI ring oscillators at cryogenic temperatures.

Findings

Significant reduction in Energy-Delay product at low temperature.

Achieved high speed (37ps) and low static power (7nA/stage) at 4.3K.

Optimal operation with V_DD reduced to 0.325V at cryogenic temperatures.

Abstract

Extensive electrical characterization of ring oscillators (ROs) made in high-$\kappa$ metal gate 28nm Fully-Depleted Silicon-on- Insulator (FD-SOI) technology is presented for a set of temperatures between 296 and 4.3K. First, delay per stage ($\tau_P$), static current ($I_{STAT}$), and dynamic current ($I_{DYN}$) are analyzed for the case of the increase of threshold voltage ($V_{TH}$) observed at low temperature. Then, the same analysis is performed by compensating $V_{TH}$ to a constant, temperature independent value through forward body-biasing (FBB). Energy efficiency optimization is proposed for different supply voltages ($V_{DD}$) in order to find an optimal operating point combining both high RO frequencies and low power dissipation. We show that the Energy-Delay product ($EDP$) can be significantly reduced at low temperature by applying a forward body bias voltage ($V_{FBB}$). We demonstrate that outstanding performance of RO in terms of speed ($\tau_P$=37ps) and static power (7nA/stage) can be achieved at 4.3K with $V_{DD}$ reduced down to 0.325V.