Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs described with Band Broadening

TL;DR

This paper investigates the saturation of subthreshold swing in 28nm FD-SOI MOSFETs at cryogenic temperatures, proposing a disorder-induced band tail model that explains experimental observations and aids future cryogenic circuit design.

Contribution

It introduces a novel disorder-induced band tail model to explain subthreshold swing saturation at cryogenic temperatures in FD-SOI MOSFETs, validated by experimental data.

Findings

Model accurately fits experimental SS(T) data from 300K to 4K.

Band tail width estimated at approximately 3 meV.

Provides a method to determine band-tail extension for cryogenic device modeling.

Abstract

In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) = \ln10~k_BT/e$. However, recent low-temperature studies of different advanced CMOS technologies have reported $SS$(4K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of $SS(T)$ in 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying Fermi-Dirac statistics. This results in a subthreshold $I_{D}\sim e^{eV_{GS}/k_BT_0}$ for $T_0=35$K with saturation value $SS(T<T_0) = \ln 10~k_BT_0/e$. The proposed model adequately describes the experimental data of $SS(T)$ from 300 down to 4K using $k_BT_0 \simeq 3$meV for the width of the exponential tail and can also accurately describe $SS(I_{D})$ within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and design of cryogenic circuits.

Equations

$$n({\Psi }_s)={\int }_{-\infty }^{\infty }f(E)N_c^{2D}(E)dE,$$

Full text

I Introduction

The development of electronic circuits at cryogenic temperatures (4 K or even lower) has great importance for a large spectrum of applications such as high-performance classical computing, cryogenic sensors and detectors, space electronics, low power neuromorphic circuits, and quantum computing [3, 1, 4, 2]. The nowadays progress in the realization of quantum bit (qubit) systems at low temperatures has proven the necessity of having nearby cryogenic electronics to enable fast and efficiently-controlled manipulation and read-out of a large number of qubits [1, 5, 6]. In this respect, the recent demonstrations of silicon qubits could be combined with state-of-the-art CMOS electronics [7, 8, 9].

The 28nm fully-depleted silicon-on-insulator (FD-SOI) MOSFETs with undoped channel have numerous advantages for low-temperature applications compared to Si bulk transistors, such as the reduced impact of dopant freeze-out, reduced variability, tuning of threshold voltage thanks to back-biasing, higher mobility, and quasi-ideal electrostatic control [11, 10].

The present study focuses on the exponential gate-voltage ($V_{GS}$) dependence of the subthreshold drain current $I_{D}$ of a MOSFET as a function of the temperature $T$ captured by the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}=m\ln 10~{}k_{B}T/e$ [12] ($SS(300~{}K)=60$ mV/dec for $m=1$), where $k_{B}$ is the Boltzmann constant and $e$ the absolute elementary charge. The factor $m=(C_{ox}+C_{it})/C_{ox}\geq 1$ takes into account the capacitance of the interface traps $C_{it}$ with respect to the geometric gate capacitance $C_{ox}$ (in our case of FD-SOI, the depletion capacitance can be neglected). The very small value of $SS$ in the (sub)K-range results in an ideal $I_{D}(V_{GS})$ switch leading to a high on/off current ratio and low power dissipation in the stand-by regime.

Cryogenic investigations of $SS(T)$ in advanced CMOS devices reveal at least one order of magnitude larger values at 4 K compared with the expected value $SS(4K)=0.79$ mV/dec for $m=1$. For bulk MOSFETs, typical values for SS(4 K) range from 30 to 10 mV/dec [13, 3, 14, 4]. Even though an effective operation of different SOI technologies at cryogenic temperature has been demonstrated, the reported SS values turned out to be as high as 7 mV/dec at 4K [15, 16, 18, 17], even at sub-1K temperatures [19].

Common explanations correlate the $SS(T)$ dependence in bulk Si transistors to an important increase of the density of interface traps $D_{it}$ close to the band edges [20]. Similarly, for planar SOI devices, the increase of $D_{it}$ has been demonstrated to extend more than 100 meV inside the band gap using the spectroscopic charge-pumping technique [21]. However, especially at the lowest temperatures, analyzing the saturation with a strongly temperature dependent increase of $m$ via $C_{it}=e^{2}D_{it}$ leads to an estimate of unrealistic $D_{it}$ values that are even larger than the silicon density of states of free carriers [19]. More recently, a constant contribution to $SS(T)$ has been derived at 4 K by modeling the thermal occupation of the interface-trap distribution  [17, 22, 23, 24] which needs temperature-specific modeling for an application to all temperatures.

In order to explain the cryogenic saturation of $SS$, we propose a new approach introducing a disorder-induced exponential tail in the density of states (DOS) for the calculation of the subthreshold charge-carrier transport. The model is validated on the experimental data of long- and short-channel MOSFETs with different oxide thicknesses in terms of both $SS(T)$ and $SS(I_{D})$ dependences from $300$ K down to $4.3$ K.

II Experiment

Thin (GO1) and thick (GO2) gate oxide low-threshold-voltage (LVT) FD-SOI transistors were fabricated with a gate-first high-$\kappa$ metal gate by STMicroelectronics on 300 mm (100) SOI wafers with a buried oxide thickness of 25nm [25, 11]. The equivalent oxide thickness (EOT) is 1.55 nm for GO1 and 3.7 nm for GO2. The 7 nm-thick channel is undoped.

Both n-type and p-type long-channel GO2 (gate length $L=0.15,2$ $\mu$m and width $W=2$ $\mu$m) and n-type short-channel GO1 ($L=28,34$ nm and $W=80,210$ nm) transistors were investigated. P-type short-channel devices couldn’t be analyzed for the $SS(T)$-dependence because of oscillatory variations in $SS(I_{D})$ below threshold at cryogenic temperatures. This results from the enhanced boron diffusion from the source/drain regions affecting subthreshold current at low $V_{DS}$ (see [26, 18]).

The transistors cleaved from a wafer were mounted to the sample holder of a cryogenic probe station equipped with 4 adjustable contact needles connected to Source/Measurement Units. Then, they were cooled down under continuous He flow with temperature regulation between 4 and 300 K. The data acquisition was done using a parameter analyzer (HP 4155A).

Fig. 1a shows $I_{D}(V_{GS})$ at temperatures between 300 and 4.3 K for the n-type long- and short-channel devices at $|V_{DS}|=50$ mV and back-gate voltage $V_{BACK}=0$ V. Both cases reveal a classical, oscillation-free $I_{D}(V_{GS})$ down to the lowest temperatures. The saturation of $SS(T)$ below about 40 K can be clearly seen from the $SS(I_{D})$ data as illustrated in Fig. 1b. The same trend holds for p-type long-channel and n-type short-channel devices.

In Fig. 1c, $SS(T)$ from 300 K down to roughly 40 K follows the expected dependence $m_{1,2}\ln 10~{}k_{B}T/e$ with $m_{1}=1.14$ for the long devices and $m_{2}=1.23$ for the short device. The slightly higher $SS$ (described by $m_{1}=1.14$) for the long devices is explained by the presence of interface traps ($C_{it}$), and the larger $m_{2}=1.23$ follows from additional electrostatic short-channel effects [27]. $SS(4.3~{}{\rm K})$ saturates at 7.3 mV/dec for n-type long-channel, 7.4 mV/dec for p-type long-channel, and 7.7 mV/dec for n-type short-channel.

III Model description and discussion

The diffusive subthreshold transport is proportional to the density $n$ of the mobile charge carriers in the channel assuming a constant diffusion constant (mobility) [12]. Using the Fermi-Dirac statistics for the occupation of electron states [27, 28], here for the n-type case, $n$ can be expressed as a function of the semiconductor potential $\Psi_{s}$ via

[TABLE]

with the Fermi function $f(E)=1/({\rm e}^{(E-E_{F})/k_{B}T}+1)$ and a step function for the two-dimensional DOS $N^{2D}_{c}(E)$ from zero to $N^{2D}_{c}=g_{v}m^{*}/\pi\hbar^{2}$ at the band edge $E_{c}=E_{c}^{0}-e\Psi_{s}$. For the flat band condition with $\Psi_{s}=0$, the Fermi energy $E_{F}$ is taken at mid-gap with $E_{c}^{0}=0.55$ eV (considering a temperature-independent energy gap 1.1 eV for Si). Other parameters are the valley degeneracy $g_{v}=2$ and the effective mass $m^{*}=0.19~{}m_{0}$ (free-electron mass $m_{0}$). Finally, the equilibrium electron density $n(\Psi_{s})$ can be transposed to $n(V_{GS})$ using $V_{GS}=\Psi_{s}+n(\Psi_{s})e/C_{ox}$ [27], for the sum of the semiconductor potential $\Psi_{s}$ and the voltage drop $ne/C_{ox}$ over the geometric gate capacitance $C_{ox}=k\epsilon_{0}/t_{EOT}$ [F/m2] supposing $m=1$. $\epsilon_{0}$ is the free-space permittivity, $k=3.9$ the relative dielectric constant of SiO2, and $t_{EOT}=3.7$ nm the equivalent oxide thickness in case of GO2.

The calculated $n(V_{GS})$ data for a sharp band edge reveal the standard exponential dependence $I_{D}\sim e^{eV_{GS}/k_{B}T}$, confirming the linear temperature dependence $SS(T)=\ln 10~{}k_{B}T/e$. However, only using the Fermi-Dirac statistics is not enough to explain the experimentally observed saturation at low temperatures as shown in Fig. 1c.

To describe the saturation of $SS$ at low temperatures, a broadened band edge [29, 30] was added to the DOS in the form $N^{2D}_{c}{\rm e}^{(E-E_{c})/k_{B}T_{0}}$ for $E<E_{c}$ (inset in Fig. 2c). The parameter $k_{B}T_{0}$ quantifies the extent of the exponential tail resulting from, e.g., crystalline disorder, residual impurities, and strain, surface roughness, etc. Assuming a proportionality between $I_{D}(V_{GS})$ and $n(V_{GS})$, the calculated $I_{D}(V_{GS})$ is shown in Fig. 2a for different temperatures with $T_{0}=35$ K (resulting in $k_{B}T_{0}=3$ meV). A saturation value $SS(T\leq T_{0})=\ln 10~{}k_{B}T_{0}/e=6.9$ mV/dec is obtained for $m=1$ (see Fig. 2b). The $3$ meV tail was determined empirically to describe the experimental $SS$(4.3 K) of 7-8 mV/dec.

To compare with the model, the saturation values $SS(T)$ in the weak inversion measured at $I_{D}=10$ pA are plotted in Fig. 2c after normalization with the corresponding $m_{1,2}$ (for the values, see Fig. 1c). It should be noted that the chosen $k_{B}T_{0}$ gives a good description of the experimental data for all studied MOSFETs. The obtained exponential extent for the band tail is comparable to that of 2-10 meV probed with Electron Spin Resonance on Si MOSFETs in [31].

FD-SOI cryogenic back-biasing was already demonstrated to be efficient down to 4 K [32]. By using forward back-biasing (FBB), the conductive channel can be displaced towards the Si-BOX interface. Therefore, if the increase of $D_{it}$ was responsible for $SS(T)$ saturation, one would expect a significant difference in $SS(I_{D})$ profiles. However, the experimental data in Fig. 3a and 3b for an n-type device at 4.3 K reveal that $SS(I_{D})$ curves hardly change for $V_{BACK}$ up to 3 V, implying that the edge-broadened DOS cannot be explained with just $D_{it}$ at the Si-SiO2 interface.

At the lowest temperatures, the measured $SS(I_{D})$ characteristics reveal an increased gate-voltage dependence (Fig. 1b) as compared to the constant $SS(I_{D})$ from our calculations (Fig. 2b). This variation of $SS(I_{D})$ can also be modeled by including an energy dependence $m(E)$ in the relation $V_{GS}(\Psi_{s})=m(\Psi_{s})\Psi_{s}+n(\Psi_{s})e/C_{ox}$, similarly to the description of the interface traps below the band edge with the additional capacitance $C_{it}$ in the introduction. In Fig. 3c the calculated $SS(I_{D})$ is shown for an exponential dependence $m(E)\sim e^{(E-E_{c})/E_{m}}$. A good agreement with the experimental data is found for a variation of $m(E)$ from 1.14 to 1.34 with an empirically-determined energy range $E_{m}=10$ meV below $E_{c}$. Regarding the physical reasoning behind the improved model which includes $m(E)$, we note that not all the states in the band tail contribute to the transport [33]. Therefore, the $V_{GS}$-induced occupation of states in the band tail influences both the subthreshold current due to mobile states and the efficiency of gate control via $m(\Psi)$ because of trapped states. In our modeling, each of these contributions has its characteristic extent in energy below $E_{c}$.

IV Conclusion

To explain the generally observed saturation of $SS$ at low temperature in FD-SOI MOSFETs, an exponential tail at the band edge is introduced yielding $I_{D}(V_{GS})$ of the form $e^{eV_{GS}/k_{B}T_{0}}$ that replaces the usual temperature dependence $e^{eV_{GS}/k_{B}T}$ for $T<T_{0}$. The determined $T_{0}=35$ K holds for all measured FD-SOI devices with long- and short-channel lengths for different oxide thickness and accurately describe the $SS(T)$ from 300 K down to 4.3 K. In addition, we address the problem of the increased cryogenic $SS(V_{GS})$ dependence at low temperatures and successfully model a non-constant $SS(I_{D})$ profile below $V_{TH}$ by introducing an energy-dependent $m(E)$ in the gate-control efficiency. Finally, our results indicate that the implementation of band-tail broadening could form an important technological parameter for the correct modeling of MOSFETs at low temperatures.