An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things

TL;DR

This paper introduces an energy-efficient, configurable lattice cryptography processor tailored for quantum-secure IoT applications, achieving significant power savings and supporting multiple post-quantum protocols in hardware.

Contribution

It presents the first ASIC implementation of a configurable lattice cryptography processor supporting multiple NIST post-quantum protocols with notable energy and area efficiency.

Findings

Two orders of magnitude energy savings over software implementations

124k-gate area reduction with single-port RAM-based NTT architecture

Supports multiple lattice-based protocols for quantum-resistant IoT security

Abstract

This paper presents a configurable lattice cryptography processor which enables quantum-resistant security protocols for IoT. Efficient sampling architectures, coupled with a low-power SHA-3 core, provide two orders of magnitude energy savings over software. A single-port RAM-based NTT architecture is proposed, which provides ~124k-gate area savings. This is the first ASIC implementation which demonstrates multiple lattice-based protocols proposed for NIST post-quantum standardization.