MIPS-Core Application Specific Instruction-Set Processor for IDEA Cryptography - Comparison between Single-Cycle and Multi-Cycle Architectures

TL;DR

This paper introduces a specialized MIPS-core processor for IDEA cryptography, comparing single-cycle and multi-cycle architectures in terms of efficiency and resource consumption, with FPGA implementation results.

Contribution

It presents a new application-specific single-cycle processor for IDEA cryptography and compares it to a multi-cycle design, highlighting resource efficiency and performance.

Findings

Single-cycle processor achieves CPI of 1.

Both architectures have similar throughput.

Single-cycle design uses fewer resources.

Abstract

A single-cycle processor completes the execution of an instruction in only one clock cycle. However, its clock period is usually rather long. On the contrary, although clock frequency is higher in a multi-cycle processor, it takes several clock cycles to finish an instruction. Therefore, their runtime efficiencies depend on which program is executed. This paper presents a new processor for International Data Encryption Algorithm (IDEA) cryptography. The new design is an Application Specific Instruction-set Processor (ASIP) in which both general-purpose and special instructions are supported. It is a single-cycle MIPS-core architecture, whose average Clocks Per Instruction (CPI) is 1. Furthermore, a comparison is provided in this paper to show the differences between the proposed single-cycle processor and another comparable multi-cycle crypto processor. FPGA implementation results show that both architectures have almost the same encoding/decoding throughput. However, the previous processor consumes nearly twice as many resources as the new one does.