Stateful Dataflow Multigraphs: A Data-Centric Model for Performance Portability on Heterogeneous Architectures

TL;DR

The paper introduces SDFGs, a data-centric intermediate representation that separates program logic from optimization, enabling performance portability across heterogeneous architectures like CPUs, GPUs, and FPGAs.

Contribution

It presents SDFGs as a novel data-centric model that simplifies optimization and portability of scientific applications on diverse hardware architectures.

Findings

SDFGs enable performance portability across CPUs, GPUs, and FPGAs.

Transformations like tiling and double-buffering improve performance.

Domain scientists can develop and port applications without modifying original code.

Abstract

The ubiquity of accelerators in high-performance computing has driven programming complexity beyond the skill-set of the average domain scientist. To maintain performance portability in the future, it is imperative to decouple architecture-specific programming paradigms from the underlying scientific computations. We present the Stateful DataFlow multiGraph (SDFG), a data-centric intermediate representation that enables separating program definition from its optimization. By combining fine-grained data dependencies with high-level control-flow, SDFGs are both expressive and amenable to program transformations, such as tiling and double-buffering. These transformations are applied to the SDFG in an interactive process, using extensible pattern matching, graph rewriting, and a graphical user interface. We demonstrate SDFGs on CPUs, GPUs, and FPGAs over various motifs --- from fundamental computational kernels to graph analytics. We show that SDFGs deliver competitive performance, allowing domain scientists to develop applications naturally and port them to approach peak hardware performance without modifying the original scientific code.