ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators

TL;DR

ROMANet is a methodology that optimizes data partitioning, scheduling, and DRAM data mapping in DNN accelerators to significantly reduce off-chip memory access energy and improve throughput.

Contribution

It introduces a novel energy-aware data management approach that minimizes DRAM accesses and exploits DRAM features for enhanced efficiency in DNN accelerators.

Findings

DRAM access energy reduced by up to 46% in tested networks.

DRAM throughput increased by 10% with ROMANet.

Significant energy savings and throughput improvements over state-of-the-art methods.

Abstract

Enabling high energy efficiency is crucial for embedded implementations of deep learning. Several studies have shown that the DRAM-based off-chip memory accesses are one of the most energy-consuming operations in deep neural network (DNN) accelerators, and thereby limit the designs from achieving efficiency gains at the full potential. DRAM access energy varies depending upon the number of accesses required as well as the energy consumed per-access. Therefore, searching for a solution towards the minimum DRAM access energy is an important optimization problem. Towards this, we propose the ROMANet methodology that aims at reducing the number of memory accesses, by searching for the appropriate data partitioning and scheduling for each layer of a network using a design space exploration, based on the knowledge of the available on-chip memory and the data reuse factors. Moreover, ROMANet also targets decreasing the number of DRAM row buffer conflicts and misses, by exploiting the DRAM multi-bank burst feature to improve the energy-per-access. Besides providing the energy benefits, our proposed DRAM data mapping also results in an increased effective DRAM throughput, which is useful for latency-constraint scenarios. Our experimental results show that the ROMANet saves DRAM access energy by 12% for the AlexNet, by 36% for the VGG-16, and by 46% for the MobileNet, while also improving the DRAM throughput by 10%, as compared to the state-of-the-art.

Tables

Table 1. TABLE I: Possible reuse priority orders for scheduling.

Order	Reuse Factors
	Highest	Medium	Lowest
1	ifmaps	weights	ofmaps
2	ifmaps	ofmaps	weights
3	weights	ifmaps	ofmaps
4	weights	ofmaps	ifmaps
5	ofmaps	ifmaps	weights
6	ofmaps	weights	ifmaps

Table 2. TABLE II: Configuration of the systolic array-based CNN accelerator.

Module	Description
Systolic Array	Size = 8 $\times$ 8 MACs
Buffers	64KB iBuff, 64KB wBuff, 64KB oBuff
	$\#$banks = 8 banks-per-buffer
Memory Controller	Policy = open row
	Scheduler = FCFS
DRAM	DDR3-1600 2Gb x8
	1 channel, 1 rank-per-channel
	1 chip-per-rank, 8 banks-per-chip
	Mode: non-burst, burst (burst length = 8)

Equations

$$\#DRA{M}_{access}=\sum _{l=1}^L\#DRA{M}_{access}^l$$

$$\begin{array}{rl}Object& ive:\underset{<T_h,T_w,T_i,T_j,T_m,T_n>}{\mathrm{minimize}}\#DRA{M}_{access}^l\\ Constr& aints:\\ & (T_h\times T_w\times T_i)\times bi{t}_{ifmaps}\le iBuff\\ & (T_p\times T_q\times T_i\times T_j)\times bi{t}_{weights}\le wBuff\\ & (T_m\times T_n\times T_j)\times bi{t}_{ofmaps}\le oBuff\end{array}$$

$$\begin{array}{rl}\#DRA{M}_{access}^l=& \#acces{s}_{ifmaps}^l+\#acces{s}_{weights}^l+\\ & \#acces{s}_{ofmaps}^l\end{array}$$

$$\begin{array}{r}R{F}_{ifmaps}^l=\lceil \frac{P^l}{str}\rceil \times \lceil \frac{Q^l}{str}\rceil \times J^l\end{array}$$

$$\begin{array}{r}R{F}_{weights}^l=\lceil \frac{H^l-P^l+1}{str}\rceil \times \lceil \frac{W^l-Q^l+1}{str}\rceil \end{array}$$

$$\begin{array}{r}R{F}_{ofmaps}^l=P^l\times Q^l\times I^l\end{array}$$

$$\begin{array}{r}{T}_{w_{last}}=W-T_w^{{}^{\prime }}-n_{T_{w_{int}}}\times \left(T_w^{{}^{\prime }}-T_{w_{ov}}\right)\end{array}$$

$$\begin{array}{r}{T}_{h_{last}}=H-T_h^{{}^{\prime }}-n_{T_{h_{int}}}\times \left(T_h^{{}^{\prime }}-T_{h_{ov}}\right)\end{array}$$

$$\begin{array}{r}{T}_{i_{last}}=I-n_{T_i}\times T_i^{{}^{\prime }}\end{array}$$

$$\begin{array}{r}{T}_{j_{last}}=J-n_{T_j}\times T_j^{{}^{\prime }}\end{array}$$

$$\begin{array}{r}{T}_{i_{last}}=I-n_{T_i}\times T_i^{{}^{\prime }}\end{array}$$

$$\begin{array}{r}{T}_m=\lceil \frac{T_h-T_p+1}{str}\rceil \end{array}$$

$$\begin{array}{r}{T}_n=\lceil \frac{T_w-T_q+1}{str}\rceil \end{array}$$

$$\begin{array}{rl}\#acces{s}_x^l& =\sum _{t=1}^{T_x}\#acces{s}_x^t\\ \text{with}x& \in \{ifmaps,weights,ofmaps\}\end{array}$$

$$\begin{array}{rl}\#acces{s}_{ifmaps}^t=& {\lceil \frac{T_h\times T_w\times T_i}{D_p}\rceil }_{rd}\end{array}$$

$$\begin{array}{rl}\#acces{s}_{weights}^t=& {\lceil \frac{T_p\times T_q\times T_i\times T_j}{D_p}\rceil }_{rd}\end{array}$$

$$\begin{array}{rl}\#acces{s}_{ofmaps}^t=& {\lceil \frac{T_m\times T_n\times T_j}{D_p}\rceil }_{rd}+\\ & {\lceil \frac{T_m\times T_n\times T_j}{D_p}\rceil }_{wr}\end{array}$$

Full text

I Introduction

Convolutional neural networks (CNNs), a particular type of deep neural networks (DNNs), have emerged as a promising solution for a wide range of machine learning applications, e.g., image classification, object detection, autonomous vehicles, and smart health-care [1]. To expedite the inference process, several CNN hardware accelerators have been proposed over the past few years[2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14]. These accelerators offer a higher performance efficiency as compared to the general-purpose CPU-based solution. However, most of them only present isolated accelerator design, and do not thoroughly study the impact of off-chip memory accesses, especially for scenarios where the full CNN processing cannot be mapped at the same time on an accelerator fabric. The reason is that the CNNs are large in size, and typical compute engine and on-chip memory are small and may not even be sufficient to process one complete layer of a network at a time. Moreover, each data is usually involved in multiple computations, i.e., multiply-and-accumulate (MAC) operations, during processing. Therefore, multiple redundant accesses for the same data to off-chip memory are inevitable.

The redundant accesses to DRAM-based off-chip memory hinder the accelerators from achieving further efficiency gains as DRAM energy is significantly higher compared to other operations [17, 18, 19], which is also shown in Fig. 1(a). Therefore, savings in DRAM energy can result in proportional system-level energy savings.

DRAM access energy is dependent on the number of accesses and the energy-per-access that varies depending upon whether the access faces a row buffer hit, a row buffer miss, or a row buffer conflict. In a row buffer hit, the requested data entity is already available in the row buffer. Hence, the data can be accessed directly without additional operation. On the other hand, a row buffer miss or conflict needs to open the requested row first before the data can be accessed. Therefore, a row buffer hit incurs less energy and latency as compared to a row buffer miss and a row buffer conflict, as shown in Fig. 1(b)-(c). From these observations, it is evident that DRAM access energy for CNN accelerators can be optimized by decreasing the number of DRAM accesses, row buffer conflicts and row buffer misses. Optimizing these parameters also lead to improved DRAM latency (and throughput) as the DRAM latency-per-access is also dependent majorly on the same parameters.

I-A The State-of-the-Art and their Limitations

Layer partitioning and Scheduling: The full CNN processing usually cannot be mapped at once on the accelerator fabric due to limited on-chip memory, i.e., $100$KB-$500$KB [17]. Therefore, layer partitioning and scheduling are required to access a portion of data from the off-chip DRAM to the on-chip accelerator fabric for computation. To reduce the DRAM accesses, previous works [3][20] employ different layer partitioning and scheduling schemes to move the data from DRAM to on-chip memory, and then reuse it multiple times for computation. Depending upon which data type111There are three data types: (1) input activations/feature maps (ifmaps), (2) output activations/feature maps (ofmaps), and (3) weights. should be kept longer on chip, previous works can be loosely classified in two categories: fixed scheduling and adaptive scheduling, which will be discussed in detail in Section II-B. In the fixed scheduling, priority of data reuse is fixed to only one data type, which is not effective to minimize the DRAM accesses, since different layers of a network may have different priority of data reuse. This limitation is addressed by the adaptive scheduling [20], the state-of-the-art scheduling which adaptively prioritizes the data reuse for each layer of a network. However, it does not consider the DRAM organization and overlapping data which should not be re-fetched again from DRAM in the analytical model for estimating the number of DRAM accesses. Therefore, the analytical model used for estimating the number of DRAM accesses is sub-optimal and has to be re-formulated.

Effective DRAM Throughput: CNN accelerators typically employ DRAM burst mode to increase the effective DRAM throughput [21, 22, 23], since it allows accessing multiple data with a single DRAM request. The state-of-the-art work [21] exploits the burst mode by mapping each data partition on continuous addresses in a DRAM bank. It prioritizes to map each data partition to different columns in the same row of the same bank. If all columns in the same row are fully filled, the remaining data are mapped in a different row of the same bank. Therefore, each data partition may occupy multiple rows in a bank. However, this mapping has a high chance to face row buffer conflicts, since data from multiple rows in a bank need to be fetched for accessing the entire data partition, thereby consuming high energy and latency. Therefore, the state-of-the-art work does not optimize the DRAM data mapping, which is crucial for CNN accelerators.

Required: These limitations hinder the CNN accelerators to achieve further energy-efficiency improvements. Therefore, there is a significant need for a methodology that optimizes (1) the number of DRAM accesses by employing effective layer partitioning and scheduling, and (2) the DRAM energy-per-access and latency-per-access by employing a DRAM mapping that effectively reduces the row buffer conflicts, while improving the DRAM throughput. However, determining the effective layer partitioning, scheduling, and DRAM mapping, pose different design challenges as discussed below.

I-B Associated Scientific Challenges

An effective layer partitioning and scheduling solution leads to the minimum number of DRAM accesses and thereby minimum energy consumption. However, the number of possible configurations can be significantly large and grows exponentially with the data size, as shown in Fig. 2. Therefore, it is necessary to efficiently explore the design space in search of the effective solution/s. Towards this, we need to formulate an optimization problem, i.e., we have to identify the constraints and formulate the design goal. Solving this problem requires an analytical model to efficiently estimate the number of DRAM accesses in an accurate manner.

I-C Our Novel Contributions

In this paper, we make the following novel contributions (illustrated in Fig. 3) to overcome the associated challenges.

We propose ROMANet methodology that enables fine-grained Reuse-driven Off-chip Memory Access management and data organization for deep neural Network accelerators. It minimizes (1) the DRAM accesses through a design space exploration that finds the effective layer partitioning and scheduling, and (2) the row buffer conflicts and misses through an effective DRAM mapping. 2. 2.

We propose an analytical model to compute the number of DRAM accesses in design space exploration for a given layer partitioning and scheduling of a layer. It models (1) the reuse factors of different data types (ifmaps, ofmaps, and weights), and (2) the layer partitioning. 3. 3.

We propose a data mapping in off-chip DRAM that prioritizes the row buffer hits, the bank- and chip-level parallelism, and exploits the DRAM multi-bank burst feature. This mechanism considers the layer partitioning and DRAM configuration, and results in the throughput improvement with less access energy and latency. 4. 4.

We propose a data mapping in on-chip SRAM buffers that exploits bank-level parallelism to efficiently shuttle data between DRAM and compute engine. This mechanism considers the layer partitioning, buffer, and compute engine configuration.

Key Results: We evaluated our ROMANet using the state-of-the-art DRAM simulators [15][16], while considering a Tensor Processing Unit [9]-based CNN accelerator. The experimental results show that, compared to the state-of-the-art technique [20], our ROMANet reduces the DRAM access energy by 12% for the AlexNet, by 36% for the VGG-16, and by 46% for the MobileNet, while improving the DRAM throughput by 10%.

I-D Paper Organization

Section II presents the preliminaries of CNNs, layer partitioning and scheduling, and DRAM fundamentals. Section III presents our ROMANet methodology. In Section IV, we discuss the evaluation methodology. Afterwards, we discuss the experimental results and our improvements over the state-of-the-art in Section V. Section VI concludes the paper.

II Preliminaries

II-A Convolutional Neural Networks

We focus on the convolutional (CONV) and fully-connected (FC) layers which are extensively used in CNNs. The pseudo-code of the convolutional operations is presented in Fig. 4. P and Q denote the height and the width of weights; M and N denote the height and the width of ofmaps; I and J denote the number of ifmaps and ofmaps; H and W denote the height and the width of ifmaps; and str denotes stride of convolution, respectively. The fully-connected operations can also be represented using the same computational loop, but by specifying the size of P, Q, H, W, M, N, and str equal to $1$.

II-B Layer Partitioning and Scheduling

The layer partitioning and scheduling of convolutional operations in a CNN are typically devised for each layer of a network, hence most of the CNN accelerators process a network sequentially, one layer at a time [5, 6, 7, 8]. The pseudo-code of a convolutional layer processing in a CNN accelerator can be represented as shown in Fig. 4(a). It has two main parts: the inner loops and the outer loops. The inner loops represent the processing of a portion of the convolutional layer whose data is available in the on-chip memory. The outer loops define the schedule of processing different portions. The size of a portion that can be processed at one time depends on the data that can be stored in the on-chip memory. Therefore, based on the size of the on-chip memory, the data can be partitioned in the form of blocks or tiles222Tiling is used as it can improves locality when there is data reuse [24]., and this is represented with the step sizes in the outer loops in Fig. 4(a). The sequence of the outer loops defines the sequence in which these tiles are moved from the DRAM to the on-chip memory to process the corresponding portions of the layer. This sequence also defines the total number of DRAM accesses required to process a layer, as the two subsequent on-chip computations can have some data in common that do not need re-fetching from the DRAM and thereby affects the total number of DRAM accesses required for inference. To minimize DRAM accesses, different layer partitioning and scheduling have been studied and employed by state-of-the-art CNN accelerators. The idea is to keep data (that has to be reused the most) longer in the on-chip memory. Depending upon which data type should be kept longer in the on-chip memory, the previous works can be loosely classified in two main categories: fixed scheduling and adaptive scheduling.

Fixed scheduling employs static tiling factors and scheduling across layers of a network, by giving priority of reuse to only one specific data type, either ifmaps, ofmaps, or weights. This concept has been widely used in previous works, such as [3]. However, if we study the reuse factors (i.e., the number of times a specific data is reused) of different data types, they vary across layers of a CNN. Therefore, a data type which has highest reuse factor in one layer can have the least reuse factor in another layer. For instance, our experimental analysis in Fig. 5 illustrates that the \nth1 layer of VGG-16 (CONV1) has the highest reuse factor for the weights, however in the \nth14 layer of VGG-16 (FC1), weights has the lowest reuse factor. This can lead to significant loss in energy efficiency, specifically when a fixed dataflow forces a data type, which has the highest reuse factor, to be fetched multiple times from DRAM, instead of keeping it longer in the on-chip memory and reusing it to the maximum level.

To address this limitation, adaptive scheduling is proposed in [20]. It employs adaptive tiling factors and scheduling, and can further reduce the DRAM accesses. However, its analytical model for estimating the number of DRAM accesses does not consider the DRAM organization and overlapping data which should not be re-fetched from DRAM. Therefore, the analytical model used for estimating the number of DRAM accesses is sub-optimal and has to be re-formulated. Furthermore, it does not consider the DRAM data organization to reduce the DRAM energy- and latency-per-access.

II-C Basic DRAM Organization and Operations

DRAM is organized into channel, rank, chip, bank, row, and column as seen from a top-down perspective (see Fig. 6).

If there is an access request to DRAM, a specific rank will respond. A rank consists of a group of chips that perform all operations in lock-step [25] [26]. The chips in a rank are accessed in parallel and contribute forming a word. Inside a chip, the request is directed to a bank and decoded into row-column addresses. An activation command with a row address triggers the row activation of this bank. Data from a row of the DRAM cells is copied to the row buffer. Afterwards, the read or write commands with a column address can be issued to the activated row buffer. If the accessed row is already activated, then the data in this row is already in the row buffer. This condition is called a row buffer hit. It skips the row activation step which results in reduction of DRAM access latency and energy. Otherwise, a row buffer miss or a row buffer conflict occurs, and the new referenced row needs to be activated. A row buffer miss means that the requested data is not available in the row buffer, since the bank does not have any row open. The bank needs to open the requested row first before the data can be accessed. Therefore, a row buffer miss requires the activation energy to activate the target row. A row buffer conflict means that another row is currently open and needs to be closed first before the bank can open the requested row. To prepare the bank for an access to a different row, precharge command is issued to trigger precharging. Then, the row activation step can be conducted. Therefore, a row buffer conflict requires precharge and activation energy.

III The ROMANet Methodology

ROMANet methodology provides a novel synergistic optimization to improve the DRAM access energy and data throughput in CNN accelerators (see Fig. 7). The overview of its operational flow is explained in the following points.

• •

Step- 1 : Determine the layer partitioning and scheduling for each layer of a network that offer the minimum DRAM accesses. However, it has to consider numerous parameters which is a non-trivial problem. To solve this, a design space exploration (DSE) is employed. The DSE requires information of the CNN (e.g., data size and stride), the DRAM (e.g., number of banks), the on-chip accelerator fabric (e.g., buffer size), and the analytical model.

In step- 1b , the DSE considers different sizes of layer partitioning for all data types, and different scheduling schemes. Towards this, we propose analytical model of layer partitioning (discussed further in Section III-A2). We also define the scheduling based on the reuse priority order from step- 1a , by analyzing the reuse factors of all data types in each layer of a network (discussed further in Section III-A1).

• •

Step- 2 : The data mapping in DRAM places each data partition across the available DRAM channels, ranks, chips, banks, rows, and columns, in a manner to maximize the row buffer hits, bank- and chip-level parallelism, and to exploit the DRAM multi-bank burst feature (discussed further in Section III-C).

• •

Step- 3 : The data mapping in SRAM buffers places each data partition across the available SRAM banks, rows, and columns, in a manner to maximize the bank-level parallelism (discussed further in Section III-D).

III-A Analytical Modeling for Estimating the Number of DRAM Accesses and Memory Mapping

In the ROMANet, there are two key solutions proposed: (1) DSE, and (2) memory mapping in DRAM and SRAM buffers. To perform DSE, we develop analytical model for (a) reuse factors, (b) layer partitioning, and (c) DRAM accesses. These models jointly provide a measure of the number of DRAM accesses that has to be minimized. Fig. 8 provides an overview regarding how these models are connected.

Design Space Reduction: We reduce the overall design space to be investigated by fixing some design parameters.

• •

We consider a CNN accelerator design based on Tensor Processing Unit (TPU) [9], with a single-level SRAM buffers hierarchy implemented using scratch-pad memory (SPM), as shown in Fig. 9. We considers SPM, since it is commonly used as the local buffer in many CNN accelerators [27].

• •

We process only a single layer of a network at one time.

• •

We also consider to process a tile of ifmaps and weights on-chip, and producing a tile of ofmaps at one time. A tile of ifmaps is defined by tiling factors $T_{h}\times T_{w}\times T_{i}$, a tile of weights is defined by $T_{p}\times T_{q}\times T_{i}\times T_{j}$, and a tile of ofmaps is defined by $T_{m}\times T_{n}\times T_{j}$, as shown in Fig. 4(b).

The Optimization Problem Formulation: We formulate the optimization problem to minimize the total number of DRAM accesses for a network ($\#DRAM_{access}$). The $\#DRAM_{access}$ is defined as the sum of the DRAM accesses from all layers of the network, expressed as

[TABLE]

The $\#DRAM_{access}^{l}$ represents the total number of DRAM accesses in layer-$l$, and $L$ represents the number of layers in the network. Since we consider to process only a single layer of a network at one time, the optimization of $\#DRAM_{access}$ can be approached by minimizing the number of DRAM accesses-per-layer ($\#DRAM_{access}^{l}$). We consider layer partitioning approach in the optimization problem, as it is employed by many CNN accelerators, such as [2][3][5][11]. Thus, the objective of the optimization is formulated as

[TABLE]

Constraints of the optimization problem are the size of on-chip buffers, because they limit the volume of data that can be stored at one time. Here, the $\#DRAM_{access}^{l}$ is defined as a sum of the number of DRAM accesses from all data types in layer-$l$, expressed as

[TABLE]

Terms $\#access_{ifmaps}^{l}$, $\#access_{weights}^{l}$, and $\#access_{ofmaps}^{l}$ represent the number of DRAM accesses in layer-$l$ for ifmaps, weights, and ofmaps, respectively. From the above equations, it is evident that to further define the model in a more fine-grained manner, the formulations need to consider modeling of different data types for calculating the reuse factors, the layer partitioning, and the DRAM accesses.

III-A1 Model of Reuse Factors

Reuse factor ($RF$) represents the number of MACs that each data entity is used for [28]. Hence, each data type has its own reuse factor in each layer of a network, which can be estimated by

[TABLE]

[TABLE]

[TABLE]

Terms $P^{l}$ and $Q^{l}$ denote the height and the width of weights; $I^{l}$ and $J^{l}$ denote the number of ifmaps and ofmaps; $H^{l}$ and $W^{l}$ denote the height and the width of ifmaps; while $str$ represents stride, respectively. Each of which is for a specific layer-$l$. The reuse factor computations for different data types are illustrated in Fig. 10.

III-A2 Model of Layer Partitioning

It is developed for all data types: (ifmaps), weights, and (ofmaps).

2.a) Input Feature Maps (ifmaps)

Depending upon the size of tiling factors, ifmaps may have many possibilities of layer partitioning. Therefore, multiple tiles may have different size and there may be overlapping data that do not require redundant fetches. Here, we observe that there are three possible access directions that can affect the modeling of layer partitioning: width-wise, height-wise, and depth-wise, as shown in Fig. 11.

Width-wise direction: In this case, tile access scheduling for width-wise direction is prioritized. For instance, if we start the access from tile-1 of ifmaps, then the sequence of access is tile-1 $\rightarrow$ tile-2 $\rightarrow$ tile-3. In this direction, there may be three types of tiles involved (i.e., tile-1, tile-2, and tile-3), which differ from each other in the tiling width ($T_{w}^{{}^{\prime}}$: base tiling width, $T_{w_{int}}$: intermediate tiling width, and $T_{w_{last}}$: last tiling width). The model is formulated as

[TABLE]

Term $n_{T_{w_{int}}}$ denotes the number of intermediate tile ($T_{w_{int}}$). The $T_{w_{int}}$ value reflects a portion of the overlapped data ($T_{w_{ov}}$) from previous fetch that should not be re-fetched again, because $T_{w_{int}}=T_{w}^{{}^{\prime}}-T_{w_{ov}}$.

Height-wise direction: In this case, tile access scheduling for height-wise direction is prioritized. For instance, if we start the access from tile-1 of ifmaps, then the sequence of access is tile-1 $\rightarrow$ tile-4 $\rightarrow$ tile-7. In this direction, there may be three types of tiles involved (i.e., tile-1, tile-4, and tile-7), which differ from each other in the tiling height ($T_{h}^{{}^{\prime}}$: base tiling height, $T_{h_{int}}$: intermediate tiling height, and $T_{h_{last}}$: last tiling height). The model is formulated as

[TABLE]

Term $n_{T_{h_{int}}}$ denotes the number of intermediate tile ($T_{h_{int}}$). The $T_{h_{int}}$ value reflects a portion of the overlapped data ($T_{h_{ov}}$) from previous fetch that should not be re-fetched again, because $T_{h_{int}}=T_{h}^{{}^{\prime}}-T_{h_{ov}}$.

Depth-wise direction: In this case, tile access scheduling for depth-wise direction is prioritized. For instance, if we start the access from tile-1 of ifmaps, then the sequence of access is tile-1 $\rightarrow$ tile-10 $\rightarrow$ tile-19. In this direction, there may be two possible types of tiles involved (i.e., tile-1 and tile-19), which differ from each other in the tiling depth ($T_{i}^{{}^{\prime}}$: base tiling depth and $T_{i_{last}}$: last tiling depth). Here, there is no intermediate tile because of no overlapping data. The model is formulated as

[TABLE]

Term $n_{T_{i}}$ denotes the number of tile $T_{i}^{{}^{\prime}}$. In summary, the tiling configuration of whole ifmaps is characterized by a combination of tiling factors $T_{h}\in\{T_{h}^{{}^{\prime}},T_{h_{int}},T_{h_{last}}\}$, $T_{w}\in\{T_{w}^{{}^{\prime}},T_{w_{int}},T_{w_{last}}\}$, and $T_{i}\in\{T_{i}^{{}^{\prime}},T_{i_{last}}\}$.

2.b) Filter Weights (weights)

For weights, the layer partitioning is characterized by $T_{p}$, $T_{q}$, $T_{i}$, and $T_{j}$ as shown in Fig. 12. Since the height and the width of weights are typically small, we simplify the $T_{p}$ and $T_{q}$ as $T_{p}=P$ and $T_{q}=Q$ to reduce the complexity of the model and design space. Therefore, there are only two possible access directions: filter set-wise direction and depth-wise direction.

Filter set-wise direction: In this case, tile access scheduling for filter set-wise direction is prioritized. The sequence of access is tile-1 $\rightarrow$ tile-2 $\rightarrow$ tile-3. In this direction, there may be two possible types of tiles involved, which differ from each other in the number of filters in a filter-set ($T_{j}^{{}^{\prime}}$: base tiling set and $T_{j_{last}}$: last tiling set). Here, there is no intermediate tile because of no overlapping data. The model is formulated as

[TABLE]

Term $n_{T_{j}}$ denotes the number of filter set $T_{j}^{{}^{\prime}}$.

Depth-wise direction: In this case, tile access scheduling for depth-wise direction is prioritized. The sequence of access is tile-1 $\rightarrow$ tile-4. In this direction, there may be two possible types of tiles involved, which differ from each other in the tiling depth ($T_{i}^{{}^{\prime}}$: base tiling depth and $T_{i_{last}}$: last tiling depth). Here, there is no intermediate tile because of no overlapping data. The model is formulated as

[TABLE]

Term $n_{T_{i}}$ denotes the number of tile depth $T_{i}^{{}^{\prime}}$. In summary, tiling configuration of weights is characterized by a combination of tiling factors $T_{p}\in\{P\}$, $T_{q}\in\{Q\}$, $T_{i}\in\{T_{i}^{{}^{\prime}},T_{i_{last}}\}$, and $T_{j}\in\{T_{j}^{{}^{\prime}},T_{j_{last}}\}$.

2.c) Output Feature Maps (ofmaps)

For ofmaps, the layer partitioning is characterized by $T_{m}$, $T_{n}$, and $T_{j}$, as illustrated in Fig. 13.

A tile of ofmaps is generated from MAC operations between a tile of ifmaps and a tile of weights at one time. Which tile of ofmaps generated from MACs, depends on which tile of ifmaps and weights that are computed. Hence, the model of ofmaps in terms of tiling height $T_{m}$ and tiling width $T_{n}$, can be formulated as

[TABLE]

[TABLE]

Meanwhile, the model for tiling depth $T_{j}$ in ofmaps follows the Eq. 10. Even though the ifmaps may have intermediate values such as intermediate height $T_{h_{int}}$ and intermediate width $T_{w_{int}}$, its MAC computations will still consider base tiling height $T_{h}^{{}^{\prime}}$ and base tiling width $T_{w}^{{}^{\prime}}$ due to overlapping data. Therefore, in ofmaps, the generated $T_{m}$ is limited to $\{T_{m}^{{}^{\prime}},T_{m_{last}}\}$ and $T_{n}$ is limited to $\{T_{n}^{{}^{\prime}},T_{n_{last}}\}$. In summary, the layer partitioning of the ofmaps is defined by combination of tiling factors $T_{m}\in\{T_{m}^{{}^{\prime}},T_{m_{last}}\}$, $T_{n}\in\{T_{n}^{{}^{\prime}},T_{n_{last}}\}$, and $T_{j}\in\{T_{j}^{{}^{\prime}},T_{j_{last}}\}$.

III-A3 Model of DRAM Accesses

Eq. 3 shows that the DRAM access-per-layer is defined as the sum of the DRAM accesses from all data types. Each of which is dependent on the layer partitioning. Therefore, the number of DRAM accesses-per-layer for each data type can be estimated as the sum of the number of DRAM accesses-per-tile, and can be formulated as

[TABLE]

Term $\#access_{x}^{t}$ represents the number of DRAM accesses-per-tile for $x$ data type ($x$ is either ifmaps, weights, or ofmaps), while $T_{x}$ denotes the number of tiles in layer-$l$, for $x$ data type. In DRAM, ifmaps and weights have only read ($rd$) type of accesses, thus their number of accesses-per-tile can be estimated as

[TABLE]

[TABLE]

Term $D_{p}$ denotes the number of DRAM chips-per-rank. Meanwhile, the ofmaps may have two types of DRAM accesses, read ($rd$) and write ($wr$). These two types exist when a tile of partial sums which are in oBuff can not be accumulated with newly generated partial sums, but they still need to be accumulated with other partial sums to produce final ofmaps. Hence, they need to be stored back to DRAM, so that the oBuff can provide space to store a new tile of partial sums. Later, this tile of partial sums has to be fetched from DRAM to complete the computation, producing a tile of final ofmaps. The generic equation to estimate the number of DRAM accesses-per-tile for ofmaps is formulated as

[TABLE]

Eq. 17 shows that the same partial sums are moved from oBuff to DRAM ($wr$) and fetched again from DRAM to oBuff ($rd$). If there is no need for transporting partial sums back to DRAM, the equation only needs to consider write ($wr$) access part for storing final ofmaps to DRAM.

III-B Proposed Design Space Exploration (DSE) for Solving the Optimization Problem

We devise an algorithm that performs an exhaustive DSE for searching the effective layer partitioning and scheduling that offer minimum DRAM accesses. The algorithm is presented in Alg. 1 and explained in the following steps.

(Step-1) For each layer of a network, we define scheduling schemes to be explored in the DSE, which are based on the reuse priority orders that are determined using Alg. 2.

In Alg. 2, the reuse factors of different data types are calculated and then sorted, so that the order of priority is known (Alg. 2: lines 3-5). The idea is to ensure that the data type with a higher reuse factor has a higher priority to be kept longer in the on-chip buffer and reused maximally for reducing the redundant accesses to DRAM. The possible orders are presented in Table I.

Therefore, a network will have reuse priority orders from all layers which can be used to define scheduling schemes for DSE (Alg. 1: line 3). For instance, if a layer has reuse priority order ofmaps $\rightarrow$ ifmaps $\rightarrow$ weights, then the corresponding scheduling is devised as shown in Fig. 14. Here, the priority is to maximally reuse ofmaps or partial sums (psums) by traversing the tile accesses of ifmaps and weights in the depth-wise direction. Therefore, the DRAM accesses for ofmaps are minimized, i.e., only for storing the final ofmaps to the DRAM. Furthermore, ifmaps should have less redundant accesses than weights, since ifmaps has higher reuse priority than weights. It is expected to be achieved by putting the tiling parameters of ifmaps (i.e., $nT_{h}$, $nT_{w}$) at the outer loop of the scheduling.

(Step-2) Fetch a tile of ifmaps and weights from DRAM, as long as they fit in the corresponding buffer (iBuff and wBuff, respectively) and can be used together in MAC operations for generating a tile of ofmaps, whose size has to fit in the oBuff (Alg. 1: lines 10-12). To define the size of a tile, we explore different combinations of tiling factors from ifmaps, weights, and ofmaps (Alg. 1: lines 6-12). Here, we consider the adjustable search steps for different tiling factors, i.e., $step_{y}$, with $y\in\{T_{h},T_{w},T_{j}\}$, to achieve faster search, as the higher search step means smaller design space to be explored. This gives trade-offs between the possible number of DRAM accesses that can be found and the DSE computation time.

(Step-3) DSE calculates the number of DRAM accesses (in Alg. 1: line 13) based on the layer partitioning and scheduling, which have been defined in the previous steps.

(Step-4) The information of layer partitioning and scheduling that offer minimum DRAM accesses is saved (Alg. 1: lines 14-22), and then used for mapping data in DRAM and buffers, which will be discussed in Section III-C and Section III-D, respectively.

Note: The DSE needs to be performed only once at the design time to find the effective partitioning and scheduling policy. Once the policy has been found, the corresponding settings in the CNN accelerator are set once during the initialization stage before performing an inference.

III-C Data Mapping in the DRAM

As the dataflow of CNN processing is known prior to the execution, it is always certain at every point during the execution that which data will be required next. Therefore, CNN execution can significantly benefit from the spatial locality. Spatial locality means that if a particular data is referenced at a particular time, it is likely that the adjacent data will be referenced in the near future. In CNN execution where the dataflow is completely known, the spatial locality can be maximized by mapping the data that will be required in the subsequent cycles together in the DRAM.

To understand the possible energy and latency values in a single DRAM access, we performed experiments to observe the energy and latency incurred by a single access in different conditions: a row buffer hit, a row buffer conflict, a row buffer miss, and an access to location in different bank in the same chip. The experimental results for energy and latency are presented in Fig. 15(a) and Fig. 15(b), respectively.

These figures show some key observations:

• •

A single DRAM access consumes standby (STBY) energy and operational energy: read (RD) or write (WR), activation (ACT), and precharge (PRE) [26].

• •

A row buffer hit requires read/write and standby energy, thereby consuming less access energy and latency compared to a row buffer conflict or a row buffer miss.

• •

A row buffer conflict requires precharge, activation, and standby energy, as it has to close the currently activated row and then open a different row. It consumes the highest access energy and latency among the observed cases.

• •

A row buffer miss requires activation and standby energy to activate the target row as there is no activated row yet.

• •

Exploiting DRAM bank-level parallelism (i.e., access to location in different bank of the same chip in a short time interval) can also be done faster and consume less energy compared to a row buffer conflict. It requires the activation, precharge and standby energy, but with less total energy than a row buffer conflict, due to its lower latency.

Furthermore, DRAM has the multi-bank burst feature that can be exploited to further improve the data throughput, as shown in Fig. 16. Therefore, we also devise the effective DRAM mapping that offers high throughput with the lowest access energy and latency.

Proposed DRAM Data Mapping: Here, multiple data from the same tile which are expected to be accessed subsequently in a short time interval, are placed in the same row of the same bank, thereby increasing the row buffer hits. To further minimize the row buffer conflicts while increasing the throughput, chip- and bank-level parallelism are exploited. Exploiting chip-level parallelism means that if multiple data from the same tile are expected to be fetched in parallel, these data are placed across chips, if applicable. Similarly, for bank-level parallelism, the data are placed across banks, if applicable. Our DRAM mapping also exploits the DRAM multi-bank burst feature to further improve the DRAM throughput. This mapping concept is illustrated in Fig. 17(a).

We further define the DRAM mapping sequence, based on our observations in Fig. 15. The proposed mapping sequence is shown Fig. 17(b). In step- 1 , we prioritize to map a data tile to different columns in the same row, to achieve maximum row buffer hits. This step can be done across different chips in parallel, if applicable, to exploit chip-level parallelism. If all columns in the same row are fully filled, then the remaining data are mapped in the different banks in the same chip, to exploit bank-level parallelism (step- 2 ). Mapping to different banks can also be done across different chips in parallel, if applicable. For each bank, data are mapped to different columns in the same row, just like step- 1 . Here, if all columns in the same row are fully filled, then the remaining data are mapped to a different row (step- 3 ). These steps
1

3 are repeated until all data are mapped in a DRAM rank. If there are remaining data left, they can be mapped in different ranks (step- 4 ) and channels (step- 5 ) respectively if applicable, using the same steps as
1

3 .

To effectively perform DRAM mapping, the information of layer partitioning and scheduling for different data types is required. Note that our DRAM mapping scheme can be employed for all DRAM variants (e.g., DDR3, DDR4, etc.), since all of them have similar internal organization, i.e., they are composed of channels, ranks, chips, banks, rows, and columns, when viewed from a top-down perspective as shown in Fig. 6 [26].

III-D Data Mapping in the SRAM Buffer

To efficiently transport the data between the DRAM and the compute engine, a data mapping in the SRAM buffer is required. Since the DRAM mapping considers tile-wise mapping, hence the SRAM buffer considers the same. Here, we employs SRAM buffer in the scratch-pad memory fashion, since it is commonly used in many CNN accelerators as the local buffer [27]. The idea of the mapping is that, if multiple data from the same tile are expected to be fetched in parallel, these data are placed across banks to exploit bank-level parallelism. Depending upon the configuration of the SRAM buffer (e.g., capacity and number of banks), we can devise an efficient data mapping.

Proposed SRAM Buffer Data Mapping: The concept of the proposed mapping is illustrated in Fig. 18. Here, we prioritize to map a data tile (for each data type) in the same row, across different banks, to achieve maximum bank-level parallelism. If the same row across different banks are fully filled, then the remaining data are mapped in a different row, across different banks. These steps are repeated until all data from the same tile are mapped in the SRAM buffer. In this manner, each tile may occupy multiple subsequent rows. For weights data type, if systolic array-based CNN accelerator is considered, different filters can be mapped in different banks, thus each bank can supply specific filter(s) to specific column of the systolic array, as illustrated in Fig. 18. Furthermore, we can also employ different sectors in the buffer, and each of which has dedicated sleep transistor to power-gate the unused sectors, for obtaining lower power and energy.

IV Evaluation Methodology

We built our experimental setup and tool flow that integrate a memory access generator, a cycle-accurate DRAM simulator, and a real experiments-based DRAM energy simulator (as shown in Fig. 19).

Memory Access Generator: Our in-house memory access generator receives the CNN information (e.g., number of layers and data size) and configuration of the DRAM and the SRAM buffers, as the inputs. It produces a DRAM access trace that represents the sequence of DRAM requests, as the output. Our tool analyzes the characteristics of CNN and extracts its reuse factor information. The reuse factor is then used for devising data scheduling, depending upon the methodology (e.g., the ROMANet uses a DSE to find the layer partitioning and scheduling). Based on the data reuse strategy, the tool generates the representative DRAM access trace.

Cycle-accurate DRAM Simulator: We used a state-of-the-art cycle-accurate DRAM simulator (i.e., Ramulator [15]) to simulate the DRAM. The input is the DRAM access trace from our memory access generator. The outputs are DRAM command trace and statistics, such as the number of accesses, operations, row buffer conflicts and row buffer misses.

DRAM Energy Simulator: To estimate the DRAM access energy for the defined DRAM requests, we used a state-of-the-art real experiments-based DRAM energy simulator (i.e., VAMPIRE [16]). The input is the DRAM command trace generated by the DRAM simulator and the output is the DRAM access energy estimation.

In this evaluation, we considered a state-of-the-art Tensor Processing Unit (TPU) [9]-like CNN hardware accelerator, as specified in Fig. 9 and Table II. We used DRAM with DDR3-1600 2Gb x8 configuration [29] [30]. Here, the DRAM open row policy was used since it keeps the row open after an access, hence the subsequent accesses to the same row can be done fast and with less energy. We considered first-come first-serve (FCFS) scheduling policy for handling DRAM requests, which totally disregards the current state of the DRAM row buffer and serves the request that is received first. We used different DRAM access modes: (1) burst mode with burst length = 8 (BL8) for DDR3 DRAM [29], which provides multiple words of data per-request, and (2) non-burst mode, which provides a single word of data per-request. For the CNNs, we used the AlexNet [31], the VGG-16 [32], and the MobileNet [33].

To study the improvements offered by the ROMANet over the state-of-the-art (or baseline) of the layer partitioning and scheduling scheme (i.e., SmartShuttle [20]), we implemented the baseline [20] and integrated it in our experimental setup. The differences between the ROMANet and the baseline are the data reuse strategy and DRAM mapping. For data reuse strategy, the baseline uses ofmaps- and weights-reuse scheduling. For DRAM mapping, since the SmartShuttle has no defined DRAM mapping scheme, we used the state-of-the-art mapping scheme from [21] for the baseline, which maps each data partition (tile) in a continuous address space in a DRAM bank to enable the effective use of the DRAM burst mode.

V Results and Discussion

V-A Reduction in the Number of DRAM Accesses

Evaluation results for the number of DRAM accesses are presented in Fig. 20(a) for the AlexNet, Fig. 20(b) for the VGG-16, and Fig. 20(c) for the MobileNet. ROMANet decreases the number of DRAM accesses by $12\%$ over the baseline for the AlexNet, by $36\%$ for the VGG-16, and by $45\%$ for the MobileNet. These improvements are achieved because of the effective layer partitioning and scheduling performed by the ROMANet, and can be associated with several aspects.

The analytical model in the ROMANet considers the overlapping data that do not need to be re-fetched from the DRAM, while the analytical model of the baseline does not consider the overlapping data. It contributes to 5% DRAM access reduction in AlexNet, 16% in VGG-16, and 21% in MobileNet. 2. 2.

The ROMANet defines the layer partitioning by exploring all possible values of tiling factors of all data types in the DSE, while the baseline employs additional rules, e.g., prioritize to maximize tiling factor $T_{j}$. 3. 3.

The ROMANet considers more possible scheduling schemes than the baseline, as they are devised from reuse factors and reuse priority orders. However, the baseline considers only the weights- and ofmaps-based scheduling schemes. It contributes to 7% DRAM access reduction in AlexNet, 20% in VGG-16, and 24% in MobileNet.

Therefore, the ROMANet considers a wider search space than the baseline, as it investigates the number of DRAM accesses in more detailed analytical model and more number of layer partitioning and scheduling schemes, which in-turn open a higher possibility to find the configuration that leads to less number of DRAM accesses. These results also show that the reductions of the DRAM accesses happen on layer-wise basis, which is in-line with the defined optimization problem.

V-B Reduction in the Number of DRAM Requests

In practice, CNN accelerators typically exploit DRAM burst mode [21, 22, 23]. Therefore, we also studied the impact of the burst mode on the number of DRAM requests, compared to non-burst mode. Evaluation results are provided in Fig. 21.

The results show that, the burst mode requires less number of DRAM requests as compared to the non-burst mode, for accessing the same number of data from DRAM. For instance, employing the burst mode with BL8 can decrease the number of DRAM requests by 8x. This is important because the burst mode only requires one-time address decoding to fetch multiple data, while the non-burst mode needs to perform address decoding each time a request is issued. Therefore, burst mode incurs less access energy than non-burst mode which will be discussed in Section V-E.

V-C Reduction in the Number of DRAM Row Buffer Conflicts and Row Buffer Misses

The evaluation results for the number of DRAM row buffer conflicts and misses are presented in Fig. 22 for the AlexNet, the VGG-16, and the MobileNet. The figure shows that, in general, our ROMANet decreases the number of DRAM row buffer conflicts and misses as compared to the baseline. For both burst mode and non-burst mode, ROMANet reduces the row buffer conflicts and misses by about $12\%$ for the AlexNet, $35\%$ for the VGG-16, and $48\%$ for the MobileNet compared to the baseline. These reductions are achieved because ROMANet devises an effective DRAM mapping policy that minimizes subsequent accesses to different rows in the same DRAM bank, when accessing a single tile partition. On the other hand, the addressing in the baseline makes the subsequent accesses to different rows in the same DRAM bank happen more frequent, when accessing a single tile partition. Therefore, it has higher possibility of row buffer conflicts than the proposed technique.

V-D Reduction in the Number of DRAM Operations

The reductions in the number of DRAM requests decrease the total number of DRAM operations, especially for read and write. Meanwhile, the reductions in the number of DRAM row buffer conflicts and misses also decrease the total number of DRAM operations, especially for activation and precharge. The reason is that, if there is no row buffer conflict or miss, then there is no need for precharging and/or activating a different row in a DRAM bank. Moreover, the open row policy keeps the currently activated row open for some time to facilitate subsequent accesses to the same row at a faster rate and with less energy consumption. Therefore, the precharge and/or activation operations are not performed and the number of DRAM operations is reduced. It is validated by the evaluation results presented in Fig. 23 for the AlexNet, the VGG-16, and the MobileNet. Each bar of the graph in these figures already includes all DRAM operations: activation, precharge, read, and write operations.

Fig. 23 shows that employing different DRAM access modes may lead to different number of operations. For both in burst mode and non-burst mode, ROMANet reduces the operations by about $12\%$ for the AlexNet, by about $34\%$ for the VGG-16, and by about $45\%$ for the MobileNet. The burst mode has less number of DRAM operations as compared to the non-burst mode, since it has less number of DRAM requests (as shown in Fig. 21). The reduction of DRAM operations is important because each operation consumes some energy. Therefore, reducing the number of DRAM operations leads to DRAM access energy savings, which will be discussed in Section V-E.

V-E DRAM Access Energy Savings

The evaluation results for the DRAM access energy are presented in Fig. 24 for the AlexNet, the VGG-16, and the MobileNet. The figure shows that, in general, our ROMANet reduces the DRAM access energy significantly as compared to the baseline, i.e., by about $12\%$ for the AlexNet, $36\%$ for the VGG-16, and $46\%$ for the MobileNet. The burst mode has less DRAM access energy as compared to the non-burst mode (about 8x energy saving), since it has less number of DRAM operations. The main sources of these savings are: 1) the reduction in the number of accesses, and 2) the reduction in the number of row buffer conflicts and misses.

The energy savings from the reduction of accesses can be observed in the figure from the reduction in the energy consumption incurred by the read and write operations. Here, read and write operations already include operations for all data types (i.e., ifmaps, ofmaps, and weights). The savings are achieved because of the effective layer partitioning and scheduling found using the design space exploration. Meanwhile, the energy savings from the reduction of row buffer conflicts and misses, are reflected by the reduction in the energy consumption incurred by the activation and precharge operations. These savings are mainly because of the effective DRAM mapping that exploits row buffer locality, to decrease the row buffer conflicts and misses. Furthermore, since the proposed mapping in ROMANet also optimizes the DRAM access latency, the standby energy is also reduced.

We also observed that, for the AlexNet and the VGG-16, the FC layers consume more access energy compared to the CONV layers, as shown in Fig. 24(a)-(b). This is due to the fact that, in these networks, the FC layers have a large number of weights compared to the CONV layers. Therefore, to access these weights, a proportional number of DRAM accesses are required, which lead to the high energy consumption shown in the figure. Meanwhile in the MobileNet, the FC layer does not dominate the DRAM access energy since the network only has a single FC layer whose number of weights and feature maps are relatively small, i.e., 1024x1000 weights, 1024 ifmaps, and 1000 ofmaps.

V-F DRAM Access Energy Savings in Sparse CNNs

To improve the energy efficiency of DNN-based systems, DNNs are usually first passed through a compression framework for achieving a compact model that can be deployed in resource constraint mobile devices [34][35]. Based on the study of different compression techniques, it has been observed that structured pruning techniques are more commonly employed due to their easy deployability using off-the-shelf libraries [34][36]. Therefore, to show the applicability of ROMANet for structurally pruned DNNs, we evaluated ROMANet for a sparse MobileNet pruned using one of the state-of-the-art structured pruning technique, i.e., AutoML for Model Compression (AMC) [34]. Fig. 25 shows the DRAM access energy per inference for the sparse MobileNet. The figure shows that our ROMANet reduces the DRAM access energy by about $30\%$ in the burst mode and by about $38\%$ in the non-burst mode, when compared to their respective baselines. The main contributors to these savings are also the reductions in the number of DRAM accesses and the number of DRAM row buffer conflicts and misses. These evaluation results prove that our ROMANet can provide DRAM access energy savings even for sparse CNNs when compared to the state-of-the-art technique.

V-G Data Throughput Improvement for DRAM Accesses

Besides optimizing DRAM access energy, our ROMANet also improves the DRAM throughput in CNN accelerators. This can be observed from the experimental results presented in Fig. 26. The figure shows that ROMANet improves the data throughput by about $10\%$ in burst mode and $1.5\%$ in non-burst mode, compared to the respective baselines. The main source of the improvement is that the proposed DRAM mapping uses bank-level parallelism to exploit DRAM multi-bank burst feature, thereby decreasing the possibility of facing row buffer conflicts. Fig. 26 also shows that throughput improvement in the burst mode is typically higher than the non-burst mode. The reason is that the non-burst mode requires higher number of DRAM operations than the burst mode for accessing the same amount of data, thereby consuming higher DRAM access latency and decreasing the benefit of exploiting DRAM multi-bank burst feature. Therefore, DRAM burst mode is preferred in practical implementation of CNN accelerators.

DRAM throughput improvement achieved by ROMANet is important because it enables fast data transfer between the off-chip DRAM and the on-chip SRAM buffers of a DNN accelerator. This is beneficial for most of the existing accelerators, such as [9][11], because the obtained DRAM throughput can fulfill the bandwidth requirement to fully utilize the on-chip compute engines, thereby maximizing their processing potential.

In general, all evaluation results (presented in Section V-A - Section V-G) show that the ROMANet methodology can provide significant DRAM access energy savings while offering a high DRAM throughput for CNN accelerators as compared to the state-of-the-art work.

VI Conclusion

We propose a novel ROMANet methodology to reduce the DRAM access energy and to improve the DRAM throughput for CNN accelerators. It leverages the knowledge of the reuse factor from a given network configuration to perform a design space exploration that finds the effective layer partitioning and scheduling that offer minimum DRAM accesses. It also exploits DRAM row buffer locality and DRAM multi-bank burst feature by employing effective DRAM data mapping. The experimental results prove that the ROMANet can reduce the number of the DRAM accesses, the row buffer conflicts and misses, as well as the operations that lead to significant DRAM access energy savings while improving the data throughput, as compared to the state-of-the-art. These results also demonstrate that a synergistic design of layer partitioning and scheduling with data mapping in memory, is important to achieve substantial energy-efficiency and throughput improvements for DRAM accesses in the CNN accelerators. Furthermore, our novel concepts would enable further studies on energy-efficient CNN accelerators.