ERSFQ 8-bit Parallel Arithmetic Logic Unit
A. F. Kirichenko, I. V. Vernik, M. Y. Kamkar, J. Walter, M. Miller, L., R. Albu, and O. A. Mukhanov

TL;DR
This paper presents the design, fabrication, and testing of a high-speed 8-bit ERSFQ ALU with wave-pipelined execution, demonstrating operation up to 2.8 GHz and detailed bias margin analysis.
Contribution
It introduces a modular, extendable 8-bit ERSFQ ALU with wave-pipelined instruction execution and comprehensive high-frequency testing capabilities.
Findings
Operates correctly up to 2.8 GHz
Bias margins of +/-11% for clock, +/-9% for instructions at low frequency
Successful fabrication with 6840 Josephson junctions
Abstract
We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling. A carry signal synchronized with an asynchronous instruction propagation provides the wave-pipeline operation of the ALU. The ALU instruction set consists of 14 arithmetical and logical instructions. It has been designed and simulated for operation up to a 10 GHz clock rate at the 10-kA/cm2 fabrication process. The ALU is embedded into a shift-register-based high-frequency testbed with on-chip clock generator to allow for comprehensive high frequency testing for all possible operands. The 8-bit ERSFQ ALU, comprising 6840 Josephson junctions, has been fabricated with MIT Lincoln Lab 10-kA/cm2 SFQ5ee fabrication process…
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