ERSFQ 8-bit Parallel Binary Shifter for Energy-Efficient Superconducting CPU

TL;DR

This paper presents the design, simulation, fabrication, and testing of an 8-bit ERSFQ binary shifter for energy-efficient superconducting CPUs, demonstrating successful operation across all shift modes with robust margins.

Contribution

It introduces a novel 8-bit ERSFQ binary shifter with asynchronous shift pulse control, fabricated with a high-kinetic inductance layer, and validated through comprehensive testing.

Findings

Successfully tested all shift modes with operational margins of +/-16%.

Demonstrated correct functionality with large data patterns within +/-10% bias margins.

Fabricated the shifter with 820 Josephson junctions using MIT Lincoln Lab process.

Abstract

We have designed and tested a parallel 8-bit ERSFQ binary shifter that is one of the essential circuits in the design of the energy-efficient superconducting CPU. The binary shifter performs a bi-directional SHIFT instruction of an 8-bit argument. It consists of a bi-direction triple-port shift register controlled by two (left and right) shift pulse generators asynchronously generating a set number of shift pulses. At first clock cycle, an 8-bit word is loaded into the binary shifter and a 3-bit shift argument is loaded into the desired shift-pulse generator. Next, the generator produces the required number of shift SFQ pulses (from 0 to 7) asynchronously, with a repetition rate set by the internal generator delay of ~ 30 ps. These SFQ pulses are applied to the left (positive) or the right (negative) input of the binary shifter. Finally, after the shift operation is completed, the resulting 8-bit word goes to the parallel output. The complete 8-bit ERSFQ binary shifter, consisting of 820 Josephson junctions, was simulated and optimized using PSCAN2. It was fabricated in MIT Lincoln Lab 10-kA/cm2 SFQ5ee fabrication process with a high-kinetic inductance layer. We have successfully tested the binary shifter at both the LSB-to-MSB and MSB-to-LSB propagation regimes for all eight shift arguments. A single shift operation on a single input word demonstrated operational margins of +/-16% of the dc bias current. The correct functionality of the 8-bit ERSFQ binary shifter with the large, exhaustive data pattern was observed within +/-10% margins of the dc bias current. In this paper, we describe the design and present the test results for the ERSFQ 8-bit parallel binary shifter.