# An ultra-low-power sigma-delta neuron circuit

## TL;DR

This paper introduces a novel sigma-delta neuron circuit in CMOS technology that significantly reduces power consumption while maintaining high signal fidelity, enabling efficient neuromorphic computing and neural network implementation.

## Contribution

It proposes a new sigma-delta neuron circuit design that overcomes limitations of existing circuits, with simulation results demonstrating improved signal-to-distortion ratio and ultra-low power consumption.

## Key findings

- Achieves up to 42 dB signal-to-distortion ratio
- Consumes orders of magnitude less energy than previous designs
- Enables mapping of real-valued RNNs to spiking neural frameworks

## Abstract

Neural processing systems typically represent data using leaky integrate and fire (LIF) neuron models that generate spikes or pulse trains at a rate proportional to their input amplitudes. This mechanism requires high firing rates when encoding time-varying signals, leading to increased power consumption. Neuromorphic systems that use adaptive LIF neuron models overcome this problem by encoding signals in the relative timing of their output spikes rather than their rate. In this paper, we analyze recent adaptive LIF neuron circuit implementations and highlight the analogies and differences between them and a first-order sigma-delta feedback loop. We propose a new sigma-delta neuron circuit that addresses some of the limitations in existing implementations and present simulation results that quantify the improvements. We show that the new circuit, implemented in a 1.8 V, 180 nm CMOS process, offers up to 42 dB signal-to-distortion ratio and consumes orders of magnitude lower energy. Finally, we also demonstrate how the sigma-delta interpretation enables mapping of real-valued recurrent neural network to the spiking framework to emphasize the envisioned application of the proposed circuit.