Towards Optimal Depth Reductions for Syntactically Multilinear Circuits

TL;DR

This paper establishes nearly optimal depth reduction bounds for syntactically multilinear circuits computing multivariate polynomials, matching known lower bounds and improving previous results, thus advancing understanding of circuit complexity.

Contribution

It provides tight upper bounds for depth-4 circuit size and general depth reductions for syntactically multilinear circuits, matching existing lower bounds and extending previous work.

Findings

Depth-4 syntactically multilinear circuits can compute any polynomial with size at most exp(O(√(n log n)))

The bounds are asymptotically optimal in the exponent for certain degrees

Results hold over all fields and extend to circuits with small individual degree

Abstract

We show that any $n$-variate polynomial computable by a syntactically multilinear circuit of size $\operatorname{poly}(n)$ can be computed by a depth-$4$ syntactically multilinear ($\Sigma\Pi\Sigma\Pi$) circuit of size at most $\exp\left({O\left(\sqrt{n\log n}\right)}\right)$. For degree $d = \omega(n/\log n)$, this improves upon the upper bound of $\exp\left({O(\sqrt{d}\log n)}\right)$ obtained by Tavenas~\cite{T15} for general circuits, and is known to be asymptotically optimal in the exponent when $d < n^{\epsilon}$ for a small enough constant $\epsilon$. Our upper bound matches the lower bound of $\exp\left({\Omega\left(\sqrt{n\log n}\right)}\right)$ proved by Raz and Yehudayoff~\cite{RY09}, and thus cannot be improved further in the exponent. Our results hold over all fields and also generalize to circuits of small individual degree. More generally, we show that an $n$-variate polynomial computable by a syntactically multilinear circuit of size $\operatorname{poly}(n)$ can be computed by a syntactically multilinear circuit of product-depth $\Delta$ of size at most $\exp\left(O\left(\Delta \cdot (n/\log n)^{1/\Delta} \cdot \log n\right)\right)$. It follows from the lower bounds of Raz and Yehudayoff (CC 2009) that in general, for constant $\Delta$, the exponent in this upper bound is tight and cannot be improved to $o\left(\left(n/\log n\right)^{1/\Delta}\cdot \log n\right)$.

Equations

$$s^{O\left(\Delta \cdot (nk/\log s{)}^{1/\Delta }\right)}.$$

$$\mathrm{Var}(u:w)+\mathrm{Var}(w)⪯\mathrm{Var}(u).$$

$$\mathrm{Var}(u:w)+\mathrm{Var}(w:v)⪯\mathrm{Var}(u:v).$$

$$\left|\mathrm{Var}(g_1)\right|\ge m\text{and}\left|\mathrm{Var}(g_2)\right|<m.$$

$$\left|\mathrm{Var}(g_1:v)\right|\ge m\text{and}\left|\mathrm{Var}(g_2:v)\right|<m.$$

$$[u]$$

$$[u:v]$$

$$[u:v]=\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u:w]\cdot [w_L]\cdot [z:v]+\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u:w]\cdot [z:v].$$

$$=[u_L]\cdot [u_R:v]$$

$$=[u_L]\cdot \left(\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u_R:w]\cdot [w_L]\cdot [z:v]+\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u_R:w]\cdot [z:v]\right)$$

$$=\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u_L]\cdot [u_R:w]\cdot [w_L]\cdot [z:v]+\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u_L]\cdot [u_R:w]\cdot [z:v]$$

$$=\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u:w]\cdot [w_L]\cdot [z:v]+\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u:w]\cdot [z:v]=\text{RHS}.$$

$$=\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u:w]\cdot [w_L]\cdot [z:v]+\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u:w]\cdot [z:v]$$

$$=[u:u]\cdot [u_L][u_R:v]=[u:v]=\text{LHS}.$$

$$=\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u:w]\cdot [w_L]\cdot [z:v]+\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u:w]\cdot [z:v]$$

$$=:T_1+T_2$$

$$T_1$$

$$=\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}\left(\sum _{i:|\mathrm{Var}(u_i)|\ge m}[u_i:w]\right)\cdot [w_L]\cdot [z:v]\text{(since [uj:w]=0 if ∣Var(uj)∣<m)}$$

$$=\sum _{i:|\mathrm{Var}(u_i)|\ge m}\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u_i:w]\cdot [w_L]\cdot [z:v].$$

$$T_2$$

$$=\sum _{\begin{array}{c}(w,z)\in {\mathcal{F}}_{m,v}^{+}\\ w\ne u\end{array}}[u:w]\cdot [z:v]+\sum _{j:|\mathrm{Var}(u_j)|<m}[u:u]\cdot [u_j:v]$$

$$=\sum _{\begin{array}{c}(w,z)\in {\mathcal{F}}_{m,v}^{+}\\ w\ne u\end{array}}\left(\sum _i[u_i:w]\right)\cdot [z:v]+\sum _{j:|\mathrm{Var}(u_j)|<m}[u_j:v]$$

$$=\sum _{\begin{array}{c}(w,z)\in {\mathcal{F}}_{m,v}^{+}\\ w\ne u\end{array}}\left(\sum _{i:|\mathrm{Var}(u_i)|\ge m}[u_i:w]\right)\cdot [z:v]+\sum _{j:|\mathrm{Var}(u_j)|<m}[u_j:v]$$

$$=\sum _{i:|\mathrm{Var}(u_i)|\ge m}\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u_i:w]\cdot [z:v]+\sum _{j:|\mathrm{Var}(u_j)|<m}[u_j:v].$$

$$=T_1+T_2$$

$$=\sum _{i:|\mathrm{Var}(u_i)|\ge m}\left(\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u_i:w]\cdot [w_L]\cdot [z:v]+\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u_i:w]\cdot [z:v]\right)$$

$$+\sum _{j:|\mathrm{Var}(u_j)|<m}[u_j:v]$$

$$=\sum _{i:|\mathrm{Var}(u_i)|\ge m}[u_i:v]+\sum _{j:|\mathrm{Var}(u_j)|<m}[u_j:v]\text{(induction)}$$

$$=[u:v]=\text{LHS}.$$

$$[u]=\sum _{(w,z)\in {\mathcal{F}}_m^{\times }}[u:w]\cdot [w_L]\cdot [z]+\sum _{(w,z)\in {\mathcal{F}}_m^{+}}[u:w]\cdot [z].$$

$$[u:v]=\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u:w]\cdot [w_L]\cdot [z:v]+\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u:w]\cdot [z:v].$$

$$[u:v]$$

$$=\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{\times }}[u:w]\cdot \left(\sum _{(p,q)\in {\mathcal{F}}_{m_w}^{\times }}[w_L:p]\cdot [p_L]\cdot [q]+\sum _{(p,q)\in {\mathcal{F}}_{m_w}^{+}}[w_L:p]\cdot [q]\right)\cdot [z:v]$$

$$+\sum _{(w,z)\in {\mathcal{F}}_{m,v}^{+}}[u:w]\cdot [z:v],$$

$$F=\sum _i\prod _j{Q}_{ij},$$

$$g=\sum _{i=1}^s\prod _{j=1}^5{g}_{i,j},$$

$$g\left(\prod _{\ell }{w}_{\ell }\right)=\sum _{i=1}^s\left(\prod _{j=1}^5{g}_{i,j}\cdot \prod _{\ell }{w}_{\ell }\right).$$

$$C^{\prime }=\sum _{i=1}^{s^{\prime }}\prod _j{g}_{ij},$$

$$s^{O\left((\Delta -1)\cdot (t/\log s{)}^{1/(\Delta -1)}\right)}=s^{O\left((\Delta -1)\cdot (nk/\log s{)}^{1/\Delta }\right)}.$$

Full text

More generally, we show that an $n$-variate polynomial computable by a syntactically multilinear circuit of size $\operatorname{poly}(n)$ can be computed by a syntactically multilinear circuit of product-depth $\Delta$ of size at most $\exp\left(O\left(\Delta\cdot(n/\log n)^{1/\Delta}\cdot\log n\right)\right)$. It follows from the lower bounds of Raz and Yehudayoff [RY09] that in general, for constant $\Delta$, the exponent in this upper bound is tight and cannot be improved to $o\left(\left(n/\log n\right)^{1/\Delta}\cdot\log n\right)$.

††footnotetext: Git info: (\gitAuthorIsoDate) , \gitAbbrevHash   \gitVtag

1 Introduction

An algebraic circuit over a field $\mathbb{F}$ and variables ${\mathbf{x}}=(x_{1},x_{2},\ldots,x_{n})$ is a directed acyclic graph whose internal vertices (called gates) are labeled as either $+$ (sum) or $\times$ (product), and leaves (vertices of indegree zero) are labeled by the variables in ${\mathbf{x}}$ or constants from $\mathbb{F}$. The gates of outdegree zero in a circuit are called its output gates. Algebraic circuits give a natural and succinct representation for multivariate polynomials; analogous to the way Boolean circuits give a succinct representation of Boolean functions. We refer the reader to the excellent survey of Shpilka and Yehudayoff [SY10] for an introduction to the area of algebraic circuit complexity. One of the main protagonists in the results in this paper will be the class of syntactically multilinear circuits which we now define.

Definition 1.1** (Syntactically Multilinear Circuits ).**

An algebraic circuit $C$ is said to be syntactically multilinear if at every product gate $v$ in $C$ with inputs $u_{1},u_{2},\ldots,u_{t}$, the set of variables in the sub-circuits rooted at $u_{i}$ are pairwise disjoint from each other.

The size of an algebraic circuit is the number of edges in it, and its depth is the length of the longest path from an output gate to a leaf. Intuitively, the size of a circuit is an indicator of the time complexity of computing the polynomial, and its depth indicates how fast the polynomial can be computed in parallel.

We now introduce a sequence of fundamental structural results for algebraic circuits, that are collectively called depth reductions; this is the main focus of this paper.

Depth Reductions.

In a beautiful, surprising and influential work, Valiant et al. [VSBR83] showed that every polynomial family which is efficiently computable by an algebraic circuit is also efficiently computable in parallel. Formally, they showed the following theorem.

Theorem 1.2** ([VSBR83]).**

There is an absolute constant $c\in\mathbb{N}$ such that the following is true. If $P$ be an $n$-variate homogeneous polynomial of degree $d$ over any field $\mathbb{F}$ which can be computed by an algebraic circuit $C$ of size $s$, then $P$ can be computed by an algebraic circuit $C^{\prime}$ (of unbounded fan-in) of depth $c\log d$ and size $(snd)^{c}$.

In particular, the theorem says that every polynomial family of polynomially bounded (in $n$) degree that is computable by a circuit of size $\operatorname{poly}(n)$ and arbitrary depth, is also efficiently computable by a circuit of size $\operatorname{poly}(\log n)$ and depth $O(\log n)$.

In a remarkable extension of Theorem 1.2, Agrawal and Vinay [AV08] showed that one can parallelize algebraic circuits even more (reducing the depth to a constant), at the cost of a larger (a non-trivial subexponential factor) blow up in the circuit size. The version of their theorem stated below is due to Tavenas [Tav15], who optimized the parameters further.

Theorem 1.3** ([AV08, Koi12, Tav15]).**

There is an absolute constant $c\in\mathbb{N}$ such that the following is true. If $P$ is an $n$-variate homogeneous polynomial of degree $d$ over any field $\mathbb{F}$ which can be computed by an algebraic circuit $C$ of size $s$, then $P$ can be computed by a homogeneous $\Sigma\Pi\Sigma\Pi$ algebraic circuit $C^{\prime}$ of size $(snd)^{c\sqrt{d}}$.

Here, a $\Sigma\Pi\Sigma\Pi$ circuit is an algebraic circuit with four layers of alternating sum and product gates with the top layer being a sum layer. Throughout this paper, when we say a depth-$4$ circuit, we mean a $\Sigma\Pi\Sigma\Pi$ circuit.

We note that while Theorem 1.3 as stated above reduces a homogeneous circuit of arbitrary depth to a homogeneous circuit of depth-$4$, but it easily follows from the proof that the depth reduction preserves syntactic restrictions. That is, if we start with a syntactically multilinear and homogeneous circuit, the resulting depth-$4$ circuit is also syntactically multilinear and homogeneous. This statement will be of particular interest as we study depth reductions for syntactically multilinear circuits in this paper.

On the optimality of reductions to depth-$4$.

An immediate consequence of Theorem 1.2 and Theorem 1.3 is that strong enough lower bounds for algebraic circuits of bounded depth imply superpolynomial lower bounds for general algebraic circuits. Thus, the questions of proving lower bounds for bounded depth circuits, and that of understanding if the parameters in Theorem 1.3 can be improved further seem to be of fundamental interest. In the last few years, we have had significant progress on both these fronts. Following a long line of work starting with a work of Kayal [Kay12] and Gupta et al. [GKKS14], we now know extremely good lower bounds for homogeneous depth-$4$ circuits.

Theorem 1.4** (Kumar and Saraf [KS17]).**

There exists a polynomial family $\{f_{n}\}$, where $f_{n}$ is a homogeneous $n$-variate polynomial of degree $d=n^{\varepsilon}$, for an absolute constant $\varepsilon>0$, such that $f_{n}$ is computable by an algebraic circuit of size $\operatorname{poly}(n)$, but any homogeneous depth-$4$ circuit computing $f_{n}$ has size $n^{\Omega(\sqrt{d})}$.

Moreover, the family $\{f_{n}\}$ is computable by a syntactically multilinear circuit of polynomial size.

If we allow the hard polynomial to be explicit but not necessarily have small circuits, then upper bound on the degree $d$ in the above theorem can be increased to as large as $n^{1-\varepsilon}$ for any constant $\varepsilon>0$.111Though this is not explicitly mentioned in these results, the proofs can be extended to this regime of parameters. Thus, in general, the exponent in the upper bound on the size of the depth-$4$ circuit obtained in Theorem 1.3 cannot be improved asymptotically. In fact, the theorem shows that we cannot even expect such an improvement for syntactically multilinear circuits in the setting when the degree $d$ is sufficiently smaller than the number of variables $n$. A natural question here is to understand if Theorem 1.3 is also asymptotically tight in the exponent when the degree is larger. The following result of Raz and Yehudayoff goes a long way towards answering this question.

Theorem 1.5** ([RY09]).**

There is a family of multilinear polynomials $\{f_{n}\}$ such that, for every $n$, the polynomial $f_{n}$ is an $n$-variate degree $d=\Theta(n)$ polynomial that can be computed by a syntactically multilinear circuit of size $\operatorname{poly}(n)$, but any multilinear circuit of depth-$4$ computing $f_{n}$ has size $n^{\Omega\left(\sqrt{n/\log n}\right)}$.

More generally, for any constant $\Delta$, any syntactically multilinear circuit of product-depth222Also referred to as a syntactically multilinear $\left(\Sigma\Pi\right)^{\Delta}$ circuit. $\Delta$ computing $f_{n}$ must have size $n^{\Omega\left((n/\log n)^{1/\Delta}\right)}$.

For depth-$4$ circuits (or $\Delta=2$), asimilar result was proved by Hegde and Saha [HS17] for the more general333A multilinear circuit is a multi-$k$-ic circuit for $k=1$. class of circuits called multi-$k$-ic circuits, where the formal degree of any variable in the circuit is bounded by a parameter $k$ (formally defined in 2.8).

Theorem 1.6** ([HS17]).**

There is an explicit family $\left\{f_{n}\right\}$ of $n$-variate multilinear polynomials of degree $d=\Theta(n)$ such that, for every $k\leq(n\log n)^{0.9}$, any multi-$k$-ic circuit of depth-$4$ computing $f_{n}$ has size at least $n^{\Omega\left(\sqrt{n/(k\log n)}\right)}$.

Thus, Theorem 1.5 and Theorem 1.6 shows that the exponent $\sqrt{d}$ in the exponent in Theorem 1.3 cannot be replaced by $o\left(\sqrt{n/\log n}\right)$. Thus, in the regime when $d=\Theta(n)$, there is a gap of $\sqrt{\log n}$ between the known lower bounds and what is potentially achievable via depth reduction. Raz and Yehudayoff [RY09] also observe that using their techniques, the lower bound cannot be improved to $n^{\omega(\sqrt{n/\log n})}$. Our main motivation for this work was to bridge this gap. In the light of Theorem 1.4, we believed the upper bound of $n^{O(\sqrt{d})}$ in Theorem 1.3 to be right bound for multilinear circuits for all $d$, and had hoped to improve the lower bound in Theorem 1.5 to $n^{\Omega(\sqrt{n})}$.

However, as we discuss next, the correct exponent for depth reduction to depth-$4$ in the high degree regime turns out to be $\sqrt{n/\log n}$. In addition to being surprising, this also offers a potentially viable approach to the question of proving superpolynomial lower bounds for syntactically multilinear circuits by extending Theorem 1.4 to the high degree regime. We now state our results and discuss the connections to multilinear circuit lower bounds.

1.1 Results

We start by stating our main theorems.

Theorem 1.7**.**

Let $C$ be a multi-$k$-ic circuit of size $s$ computing a polynomial in $n$ variables. Then, there is a multi-$k$-ic $\Sigma\Pi\Sigma\Pi$ circuit $C^{\prime}$ of size $s^{O\left(\sqrt{\frac{kn}{\log s}}\right)}$ computing the same polynomial.

Theorem 1.8**.**

Let $C$ be a multi-$k$-ic circuit of size $s$ computing a polynomial in $n$ variables. Then, there is a multi-$k$-ic $(\Sigma\Pi)^{\Delta}$ circuit $C^{\prime}$ computing the same polynomial whose size is at most

[TABLE]

Thus, for $s=\operatorname{poly}(n)$, $k=o(\log s)$ and $n\geq d\geq\omega\left(\frac{kn}{\log s}\right)$, the exponents in the upper bounds in Theorem 1.7 are asymptotically better than that in Theorem 1.3. An immediate consequence of Theorem 1.7 is the following corollary.

Corollary 1.9**.**

Let $\{f_{n}\}$ be an explicit family of multilinear polynomials, such that $f_{n}$ is an $n$ variate polynomial of degree $d=\omega(n/\log n)$, and any multilinear $\Sigma\Pi\Sigma\Pi$ circuit computing $f_{n}$ has size at least $n^{\Omega(\sqrt{d})}$. Then, $\{f_{n}\}$ requires superpolynomial size syntactically multilinear circuits.

The corollary is of interest since by Theorem 1.4, we know $n^{\Omega(\sqrt{d})}$ lower bounds for homogeneous multilinear $\Sigma\Pi\Sigma\Pi$ circuits, when $d=n^{\varepsilon}$. Thus extending these bounds so that they hold for higher degree polynomials will imply superpolynomial lower bounds for multilinear circuits. The current best lower bound known for multilinear circuits is a nearly quadratic lower bound in a recent work of Alon et al. [AKV18]. The standard technique for proving lower bounds for multilinear models is via the rank of the partial derivative matrix under a random partition of variables (due to Raz [Raz09]). This has been useful in almost all of the known lower bounds for multilinear models, such as super polynomial lower bounds for multilinear formulas [Raz09], exponential lower bounds for constant depth multilinear circuits [RY09] as well as the currently known superlinear and nearly quadratic lower bounds for multilinear circuits [RSY08, AKV18]. However, this technique is too weak to yield even super-cubic lower bounds for syntactically multilinear circuits. Thus, currently we do not even have potential approaches to proving superpolynomial lower bounds for multilinear circuits. In the light of this, it certainly seems worth exploring if the partial derivative based methods used in the proof of Theorem 1.4 can be extended to work for multilinear polynomials whose degree $d=\omega(n/\log n)$ is high. As far as we understand, there does not seem to be strong evidence one way or the other about this.

For multi-$k$-ic circuits, we do not even know superpolynomial lower bounds for formulas or even constant depth formulas. Based on the discussion above, Theorem 1.7 does seem to offer a potentially viable approach to prove these lower bounds.

Finally, we note again that the upper bound on the size of the depth-$4$ circuit obtained in Theorem 1.7 cannot be further improved asymptotically in the exponent as Theorem 1.5 shows.

1.2 Proof Overview

We focus on giving an outline of the proof of Theorem 1.7 for the multilinear case (or $k=1$). The proof follows the strategy of the proof of Theorem 1.3 with some key differences, which we point out as we go along. There are two main steps and we now give an sketch of both of them.

Balancing a syntactically multilinear circuit.

For this step, the key notion is that of a balanced circuit. We say that a circuit $C$ is balanced with respect to a potential function $\Phi:C\rightarrow\mathbb{N}$ (e.g. degree, number of variables), if the fan-in of every product $g$ in $C$ is a constant, and $\Phi(g)\geq 2\Phi(h)$ for every child $h$ of $g$. In the proof of Theorem 1.3, the authors essentially use the results of Valiant et. al. [VSBR83] to balance a homogeneous circuit with the potential function $\Phi$ being the formal degree of a gate. For our proof, we show that a syntactically multilinear circuit can in fact be balanced with the potential function being the number of variables in the sub-circuit rooted at a gate. Our proof of this part involves the machinery of gate quotients and frontier decompositions developed by Valiant et al. in their original proof, although there are some crucial differences which require some non-trivial (albeit simple) insights.

One such challenge stems from the fact that while in a homogeneous circuit, the formal degree of any two children of a product gate is the same and equal to the formal degree of the parent, where as the children might depend on very different (even completely disjoint) sets of variables. To get around this, our notion of frontier is different from that of Valiant et al [VSBR83]. In [VSBR83], frontier is defined with respect to vertices, whereas we define frontier with respect to edges. As a consequence, our frontier decomposition statements are slightly different from those in [VSBR83], although they continue to have a natural semantic meaning. This is detailed in Section 5.

Reduction to depth-$4$ from a balanced circuit.

In the second part of our proof, we show that any balanced syntactically multilinear circuit of size $s$ computing a polynomial in $n$ variables can be depth reduced to a syntactically multilinear depth-$4$ circuit of size $s^{O(\sqrt{n/\log n})}$. The proof is along the lines of the proof of the analogous statement in the homogeneous (non-multilinear) setting by Chillara et. al. [CKSV16]. The high level idea of the proof is the following : in a balanced circuit $C$, the polynomial computed at any gate $g$ can be written as a sum of product of terms, where the product fan-in is a constant, the sum fan-in is upper bounded by the size of the circuit, and the number of variables in any of the terms is at most half of the number of variables in $g$. Moreover, each of the terms is a polynomial computed by a gate in $C$, so this decomposition can be recursively applied. We apply this decomposition repeatedly till every term in the sum of products expression of the output depends on at most $t$ variables. We argue that the sum fan-in of this sum of products expression is at most $s^{O(n/t)}$. Now, we expand each of the terms (which is a multilinear polynomial) as a sum of multilinear monomials in $t$ variables. Thus, the total size of the $\Sigma\Pi\Sigma\Pi$ circuit obtained is $2^{t}\cdot s^{O(n/t)}$ which is $s^{O(\sqrt{n/\log s})}$ for $t=\sqrt{n\log s}$.

In the proof of the analogous statement for homogeneous non-multilinear circuits, at the end of the repeated applications of the decomposition, each of the terms is of degree at most $t$. Thus, a sum of product expansion of each such term has size $\binom{n}{t}$, and so the total size of the $\Sigma\Pi\Sigma\Pi$ circuit obtained is $n^{t}\cdot s^{O(n/t)}$, which for $s=\operatorname{poly}(n)$ is minimized for $t=\sqrt{n}$ and equals $s^{O(\sqrt{n})}$. This explains the gain in the size obtained by Theorem 1.7.

2 Preliminaries

In this section, we describe the notion of proof-trees and gate quotients which are crucial to our proof and set up some of the machinery we need for the proof.

2.1 Proof-trees and quotients

Definition 2.1** (Proof-trees).**

Let $C$ be an algebraic circuit. For any $u_{0}\in C$, a proof-tree $T$ rooted at $u_{0}$ is a subcircuit of $C$ that satifies the following properties:

• •

the node $u_{0}\in T$,

• •

if $u\in T$ is a multiplication gate of $C$ with $u=v_{1}\times v_{2}$, then $v_{1},v_{2}$ are also in $T$,

• •

if $u\in T$ is an addition gate of $C$ with $u=v_{1}+v_{2}$, then exactly one of $v_{1}$ or $v_{2}$ is in $T$.

Any such sub-circuit computes just a monomial, and this shall be called the value the proof-tree. Although the proof-tree defined above need not be a tree, it shall unfolded to a tree.

If $T$ is a proof-tree rooted at $u$, and $v$ is a node that appears on its right-most path, then the tree $T^{\prime}$ obtained by replacing $v$ only on the right-most path by a leaf labelled $1$ is said to be a $v$-snipped proof-tree rooted at $u$.

Definition 2.2** ($\operatorname{Var}$ operator).**

For any nodes $u\in C$, we denote by $\operatorname{Var}(u)$ the vector $(d_{1},\ldots,d_{n})\in\mathbb{N}_{\geq 0}^{n}$ where $d_{i}$ is the maximum $x_{i}$-degree over all proof-trees rooted at $u$.

Similarly, for any pair of nodes $u,v\in C$, we denote by $\operatorname{Var}(u:v)$ the vector $(d_{1},\ldots,d_{n})$ where $d_{i}$ is the maximum $x_{i}$-degree over all $v$-snipped proof-tree rooted at $u$.

We shall also define $\left|(d_{1},\ldots,d_{n})\right|=\sum d_{i}$.

For a multilinear circuit $C$, note that $\left|\operatorname{Var}(g)\right|$ for any gate $g\in C$ is precisely the number of distinct variables in the sub-circuit rooted at $g$.

Remark 2.3**.**

Throughout this discussion, we will assume that the circuit is right heavy. This means that for every multiplication gate, $w=w_{L}\times w_{R}$, $\operatorname{Var}(w_{R})\geq\operatorname{Var}(w_{L})$. Note that this is without loss of generality, since left and right are merely labels that we can assign arbitrarily to the children of every gate in the circuit.

Definition 2.4** (Gate Quotient).**

For every two gates $u,v$ in $C$, the gate quotient of $u$ with respect to $v$, denoted by $[u:v]$ is defined inductively as follows.

• •

If $u=v$, then $[u:v]=1$.

• •

If $u=u_{1}+u_{2}$, then $[u:v]=[u_{1}:v]+[u_{2}:v]$.

• •

If $u=u_{L}\times u_{R}$, then $[u:v]=[u_{L}][u_{R}:v]$.

• •

If $v$ does not appear in the subcircuit rooted at $u$, then $[u:v]=0$.

Lemma 2.5**.**

Let $u,v\in C$. Then, the polynomial $[u]$ is the sum of values of all proof-trees rooted at $u$. Furthermore, the polynomial $[u:v]$ is the sum of the value of all $v$-snipped proof-trees $T$ rooted at $u$.

The above lemma is almost folklore and a proof of it can be seen in the work of Allender et. al. [AJMV98].

2.2 Syntactic restrictions on proof-trees

We remark that throughout this paper, by degree, we mean the syntactic or formal degree, which could be much larger than the actual or semantic degree. The following observation records some basic properties of the $\operatorname{Var}$ operator.

Observation 2.6**.**

Let $C$ be any algebraic circuit. Then,

• •

$\operatorname{Var}(u)$* is monotonically non-increasing as $u$ moves towards the leaves. That is, if $u$ is an ancestor of $v$, then ever coordinate of $\operatorname{Var}(u)$ is at least as large as the corresponding coordinate in $\operatorname{Var}(v)$.*

Similarly, for any fixed $v$, the vector $\operatorname{Var}(u:v)$ is monotonically non-increasing as $u$ moves towards the leaves.

• •

For any multiplication gate $u=u_{1}\times u_{2}$, we have $\operatorname{Var}(u)=\operatorname{Var}(u_{1})+\operatorname{Var}(u_{2})$. Similarly for any $v$, we have $\operatorname{Var}(u:v)=\operatorname{Var}(u_{1})+\operatorname{Var}(u_{2}:v)$.

• •

For any addition gate $u=u_{1}+u_{2}$, we have $\operatorname{Var}(u)=\max(\operatorname{Var}(u_{1}),\operatorname{Var}(u_{2}))$, the coordinate-wise max of the two vectors. Similarly for any $v$, $\operatorname{Var}(u:v)=\max(\operatorname{Var}(u_{1}:v),\operatorname{Var}(u_{2}:v))$.

Proof.

The proofs immediately follow from the definitions. ∎

For two vectors $\mathbf{v}_{1},\mathbf{v}_{2}\in\mathbb{N}_{\geq 0}^{n}$, we shall say $\mathbf{v}_{1}\preceq\mathbf{v}_{2}$ if each coordinate of $\mathbf{v}_{1}$ is at most the corresponding coordinate in $\mathbf{v}_{2}$.

Observation 2.7**.**

Suppose $u\in C$ and $w$ is a node in $C$ such that there is some proof-tree rooted at $u$ with $w$ appearing on its rightmost path. Then,

[TABLE]

Similarly, suppose $w$ is a node in $C$ such that there is some $v$-proof-tree rooted at $u$ with $w$ appearing on its rightmost path. Then,

[TABLE]

Proof.

The proof is straightforward; we just give the proof of the second equation. Fix a coordinate $i$. If $d_{i}=(\operatorname{Var}(u:w))_{i}$ then there is some $w$-snipped proof-tree $T_{i}$ rooted at $u$ whose $x_{i}$-degree equals $d_{i}$. Similarly if $e_{i}=(\operatorname{Var}(w:v))_{i}$, then there is some $v$-snipped proof-tree rooted $T_{i}^{\prime}$ rooted at $w$ whose $x_{i}$-degree is $e_{i}$. Clearly the gluing of $T_{i}$ and $T_{i}^{\prime}$ obtained by replacing the snipped vertex $w$ in $T_{i}$ with the tree $T_{i}^{\prime}$ is a $v$-snipped proof-tree rooted at $u$ with $x_{i}$-degree $d_{i}+e_{i}$. Therefore $d_{i}+e_{i}\leq(\operatorname{Var}(u:v))_{i}$ and the claim follows. ∎

Definition 2.8** (Syntactically multilinear and multi-$k$-ic circuits).**

A circuit $C$ is said to be syntactically multilinear if $\operatorname{Var}(u)\in\left\{0,1\right\}^{n}$ for all $u\in C$.

A circuit $C$ is said to be syntactically multi-$k$-ic if $\operatorname{Var}(u)\in\left\{0,1,\ldots,k\right\}^{n}$ for all $u\in C$.

3 Frontier edges and quotient

Definition 3.1** (Frontier edges).**

For a circuit $C$, an edge between two gates $g_{1},g_{2}$ (where $g_{1}$ is the parent) is said to be an $m$-frontier edge (for a parameter $m$) if

[TABLE]

We will use $\mathcal{F}_{m}^{\times}$ to denote the set of all $m$-frontier edges $(g_{1},g_{2})$ where $g_{1}$ is a multiplication gate, and $\mathcal{F}_{m}^{+}$ to denote those where $g_{1}$ is an addition gate.

Furthemore, if $v\in C$ is a fixed gate, we shall say that $(g_{1},g_{2})$ is an $m$-frontier edge with respect $v$ if

[TABLE]

We will use $\mathcal{F}_{m,v}^{\times}$ to denote the set of all edges $(g_{1},g_{2})$ that are $m$-frontier edges with respect to $v$ where $g_{1}$ is a multiplication gate, and $\mathcal{F}_{m,v}^{+}$ to denote those where $g_{1}$ is an addition gate.

4 Decomposition via gate quotients

In this section, we prove the following lemma, which is the key technical observation needed for our proofs.

Lemma 4.1**.**

Let $u,v$ be gates in an algebraic circuit $C$ with $\left|\operatorname{Var}(u)\right|\geq m$ and $\left|\operatorname{Var}(v)\right|<m$. Then,

[TABLE]

Before giving the formal proof, we shall give an informal sketch using the concept of proof-trees. For any $u,v$, we have that $[u:v]$ is the sum of all $v$-snipped proof-trees rooted at $u$. For any proof-tree, since $\left|\operatorname{Var}(u)\right|\geq m$ and $\left|\operatorname{Var}(v)\right|<m$ and $\operatorname{Var}(\cdot)$ is a monotonically non-increasing function as we move towards the leaves, there must be a unique edge $(w,z)\in\mathcal{F}_{m,v}^{\times}\cup\mathcal{F}_{m,v}^{+}$ on its right-most path such that $\left|\operatorname{Var}(w)\right|\geq m$ and $\left|\operatorname{Var}(z)\right|<m$.

If $(w,z)\in\mathcal{F}_{m,v}^{\times}$, then $w=w_{L}\times z$ is a multiplication gate. Therefore, the sum of the values of all $v$-snipped proof-trees with $w$ (and hence the edge $(w,z)$) on its rightmost path is exactly $[u:w][w:v]=[u:w][w_{L}][z:v]$.

If $(w,z)\in\mathcal{F}_{m,v}^{+}$, then $w=w_{1}+z$ is an addition gate. Then, $[u:w]\cdot[w:v]$ is the sum of all $v$-snipped proof-trees with $w$ on its rightmost path and $[u:w][w:v]=[u:w][w_{1}:v]+[u:w][z:v]$. Each $v$-snipped proof-tree with $w$ on its rightmost path either has $(w,w_{1})$ on the rightmost path or $(w,z)$. The term $[u:w][w_{1}:v]$ is precisely the sum of the values of such444$v$-snipped proof-trees rooted at $u$ that have $w$ on its rightmost path proof-trees with $(w,w_{1})$ on its rightmost path, and $[u:w][z:v]$ is precisely the sum of the values of those proof-trees with $(w,z)$ on its rightmost path.

Since the rightmost path of any $v$-snipped proof-tree rooted at $u$ has a unique edge $(w,z)\in\mathcal{F}_{m,v}^{\times}\cup\mathcal{F}_{m,v}^{+}$, summing over all such potential edges gives

[TABLE]

The proof below is just a formalisation of the above sketch.

Proof of 4.1.

The proof shall proceed by induction on the height of $u$ (leaves are at height [math]). We shall present the proof of (4.3); the proof of (4.2) is analogous.

Case $1$: $u=u_{L}\times u_{R}$

For any $w$, we have that $[u:w]=1$ if $u=w$, and $[u:w]=[u_{1}]\cdot[u_{2}:w]$ whenever $u\neq w$. In particular, since $\left|\operatorname{Var}(v)\right|<m\leq\left|\operatorname{Var}(u)\right|$ the LHS is $[u:v]=[u_{L}]\cdot[u_{R}:v]$.

If $\left|\operatorname{Var}(u_{R})\right|\geq m$, then for any $(w,z)\in\mathbb{F}_{m,v}^{+}$ or $\mathcal{F}_{m,v}^{\times}$ we have $w\neq u$. Inducting on $u_{R}$,

[TABLE]

On the other hand, if $\left|\operatorname{Var}(u_{R})\right|<m$ then $[u:w]=0$ for any $w\neq u$ with $\left|\operatorname{Var}(w)\right|\geq m$. Hence,

[TABLE]

Case $2$: $u=u_{1}+u_{2}$

For any $w$, we have that $[u:w]=1$ if $u=w$, and $[u:w]=[u_{1}:w]+[u_{2}:w]$ whenever $u\neq w$. In particular, since $\left|\operatorname{Var}(v)\right|<m\leq\left|\operatorname{Var}(u)\right|$ the LHS is $[u:v]=[u_{1}:v]+[u_{2}:v]$.

Since $u$ is a $+$ gate, $(u,u_{j})\notin\mathcal{F}_{m,v}^{\times}$ for any $j$. If $\left|\operatorname{Var}(u_{j})\right|<m$ for some $j$, then the edge $(u,u_{j})\in\mathcal{F}_{m,v}^{+}$. Hence,

[TABLE]

In $T_{1}$, since every $(w,z)\in\mathcal{F}_{m,v}^{\times}$ has $w\neq u$ we have

[TABLE]

As for the other term, it can be written as

[TABLE]

The last equality holds because $[u_{i}:u]=0$. Putting it together,

[TABLE]

∎

5 Balancing syntactically multilinear circuits

In this section, we prove the following theorem.

Theorem 5.1**.**

Suppose $C$ is an algebraic circuit of size $s$. Then, there is a circuit $C^{\prime}$ of size $\operatorname{poly}(s)$ computing the same polynomial with the following structural properties.

• •

all addition gates in $C^{\prime}$ have fan-in $O(s^{4})$,

• •

all multiplication gates in $C^{\prime}$ have fan-in at most $5$,

• •

for any multiplication gate $g\in C^{\prime}$, any child $h$ of $g$ satisfies $\left|\operatorname{Var}(h)\right|\leq\left|\operatorname{Var}(g)\right|/2$.

Furthermore, if $C$ is syntactically multi-$k$-ic, then so is $C^{\prime}$.

Proof.

Without loss of generality, we may assume that the circuit is right-heavy in the sense that for every multiplication gate $u=u_{1}\times u_{2}$ we have $\left|\operatorname{Var}(u_{2})\right|\geq\left|\operatorname{Var}(u_{1})\right|$. We shall build a new circuit $C^{\prime}$ that computes all $[u:v]$’s and $[u]$’s for gates $u,v\in C$ using the equations in 4.1.

We shall assume inductively that we have already computed all $[w]$’s with $\left|\operatorname{Var}(w)\right|<t$ and also all $[w,v]$ with $\left|\operatorname{Var}(w,v)\right|<t$. Suppose $u\in C$ such that $\left|\operatorname{Var}(u)\right|=t$. Using (4.2) from 4.1 with $m=t/2$ we have

[TABLE]

By 2.7, $\left|\operatorname{Var}(w)\right|\geq t/2$ implies that $\left|\operatorname{Var}(u:w)\right|\leq t/2$. Furthermore, $\left|\operatorname{Var}(z)\right|\leq t/2$ by the choice of the frontier edge and $\left|\operatorname{Var}(w_{L})\right|\leq t/2$ since $C$ is right-heavy. This allows us to compute all nodes of the form $[u]$ with $\left|\operatorname{Var}(u)\right|\leq t$.

If $u,v\in C$ such that $\left|\operatorname{Var}(u:v)\right|=t$. Using (4.3) from 4.1 with $m=t/2$, we have

[TABLE]

We can restrict the edges in the RHS to only those edges $(w,z)$ that is present in at least one $v$-snipped proof-tree rooted at $u$ (if not, this edge’s contribution to the RHS is zero). Therefore by 2.7, $\operatorname{Var}(w:v)+\operatorname{Var}(u:w)\preceq\operatorname{Var}(u:v)$ and therefore we have $\left|\operatorname{Var}(u:w)\right|\leq t/2$. Furthermore, by the choice of the frontier, we also have $\left|\operatorname{Var}(z:v)\right|\leq t/2$. The non-trivial case is $\operatorname{Var}(w_{L})$ which could in principle be large but again $\operatorname{Var}(w_{L})\preceq\operatorname{Var}(w:v)\preceq\operatorname{Var}(u:v)$ as any proof-tree rooted $w_{L}$ is a sub-tree of a $v$-snipped tree rooted at $u$. Since we have already computed all gates $[w]$ with $\operatorname{Var}(w)\leq t$, we can write

[TABLE]

where $m_{w}=\operatorname{Var}(w_{L})/2$.

The required structural properties of $C^{\prime}$ are readily seen from the above construction. ∎

6 Reduction to depth four from balanced circuits

We now show how to reduce a balanced circuit to a depth-$4$ circuit. This would complete the proof of our main theorem. We shall use the notation $\Sigma\Pi\left(\Sigma\Pi\right)_{t}$ to refer to $\Sigma\Pi\Sigma\Pi$ circuits computing polynmomials of the form

[TABLE]

with $\left|\operatorname{Var}(Q_{ij})\right|\leq t$.

The proof of this part follows the outline of a similar argument in Chillara et. al. [CKSV16] of reducing to depth-$4$ from a balanced circuit. However, there are some differences: our potential is $\left|\operatorname{Var}(\;\cdot\;)\right|$ and not the degree (as is usually the case). Since this potential function also falls as we go from a sum $(+)$ gate to its children, we need one more simple observation in our argument to bound the number of steps in the recursion in the proof. We now provide the details.

Lemma 6.1**.**

Let $C$ be a multi-$k$-ic circuit of size $s$ such that every multiplication gate $g$ in $C$ fan-in at most $5$ and for every child $h$ of $g$ in $C$, $\operatorname{Var}(h)\leq\operatorname{Var}(g)/2$.

Then, for any positive integer $0\leq t\leq kn$, there is an equivalent multi-$k$-ic $\Sigma\Pi\left(\Sigma\Pi\right)_{t}$ circuit $C^{\prime}$ that computes the same polynomial, with the following properties:

• •

the top fan-in of $C^{\prime}$ is at most $s^{O(kn/t)}$,

• •

the size of $C^{\prime}$ is at most $2^{kt}\cdot s^{O(kn/t)}$,

• •

each of the $(+)$-gates closer to the leaves compute polynomials that computed by gates in $C$.

Proof.

Since $C$ is balanced, with product fan-in at most $5$, every gate $g$ in $C$ can be written as

[TABLE]

where each $g_{i,j}$ is also computed by a gate in the circuit $C$, $|\operatorname{Var}(g_{i,j})|\leq|\operatorname{Var}(g)|/2$. With this notation, (6.2) applied on the root of $C$ says that $C$, which is a syntactically multi-$k$-ic circuit, can be trivially written as a $\Sigma\Pi\left(\Sigma\Pi\right)_{kn/2}$. A natural idea would be to apply (6.2) on the $g_{i,j}$’s until we get a $\Sigma\Pi\left(\Sigma\Pi\right)_{t}$ circuit. All that is needed is to bound the number of summands (or the top fan-in of the resulting $\Sigma\Pi\left(\Sigma\Pi\right)_{t}$ circuit) at the end of this process. Observe that for every $i\in\{1,2,\ldots,s\}$, we could have that $\left|\operatorname{Var}(\prod_{j=1}^{5}g_{i,j})\right|$ is much smaller than $\left|\operatorname{Var}(g)\right|$ itself.

We will view the process as a tree in the natural way. The root of the tree corresponds to the root of the circuit, and all other nodes in the tree correspond to products of addition gates in $C$. The children of a node in the tree correspond to the summands in the sum of product representation of that node obtained by expanding one of its factors according to (6.2). The leaves of this tree are products of addition gates $\prod g_{i}^{\prime}$ such that $\left|\operatorname{Var}(g_{i}^{\prime})\right|\leq t$ for each factor $g_{i}^{\prime}$. The tree has a branching factor of at most $s$, hence it suffices to get a bound on the depth of the tree to get a bound on the number of leaves which would be the top fan-in of the $\Sigma\Pi\left(\Sigma\Pi\right)_{t}$ representation.

Let $g\prod_{\ell}w_{\ell}$ be an internal node in the tree with $\left|\operatorname{Var}(g)\right|>t$. After applying (6.2) on $g$, we get

[TABLE]

We now consider two cases.

• •

$\left|\operatorname{Var}\left(\prod_{j=1}^{5}g_{i,j}\right)\right|<3t/4$** :** In this case, $\left|\operatorname{Var}\left(\prod_{j=1}^{5}g_{i,j}\cdot\prod_{\ell}w_{\ell}\right)\right|\leq\left|\operatorname{Var}\left(g\cdot\prod_{\ell}w_{\ell}\right)\right|-t/4$.

• •

$\left|\operatorname{Var}\left(\prod_{j=1}^{5}g_{i,j}\right)\right|\geq 3t/4$** :** Since $\operatorname{Var}(g)\succeq\operatorname{Var}(g_{i,1}\cdots g_{i,5})=\operatorname{Var}(g_{i,1})+\cdots+\operatorname{Var}(g_{i,5})$ and $\left|\operatorname{Var}(g_{i,j})\right|\leq t/2$, it follows that the number of factors $h$ in $\prod_{j=1}^{5}g_{i,j}\cdot\prod_{\ell}w_{\ell}$ with $\left|\operatorname{Var}(h)\right|\geq t/16$ is at least one more than the number of such factors in $g\cdot\prod_{\ell}w_{\ell}$. This is because besides the factor $g_{i,j}$ with largest $\left|\operatorname{Var}(g_{i,j})\right|$, the other four factors together must contribute at least $(3t/4)-(t/2)=(t/4)$ to $\left|\operatorname{Var}(g_{i,1}\cdots g_{i,5})\right|$ and hence at least one of them must have $\left|\operatorname{Var}(g_{i,k})\right|\geq t/16$.

Thus, in any edge of the tree, either $\left|\operatorname{Var}(\;\cdot\;)\right|$ decreases by $t/4$ or the number of factors with $\left|\operatorname{Var}(\;\cdot\;)\right|\geq t/16$ increases by one. The root node $g_{0}$ has $\left|\operatorname{Var}(g_{0})\right|\leq kn$. Hence, the depth of the tree is bounded by $(16+4)(kn/t)=O(nk/t)$. Therefore, $C$ can be computed by a syntactically multi-$k$-ic $\Sigma\Pi\left(\Sigma\Pi\right)_{t}$ circuit of top fan-in at most $s^{O(nk/t)}$.

To get the bound on the overall size of the $\Sigma\Pi\left(\Sigma\Pi\right)_{t}$ circuit, we need to bound the sparsity of the polynomials computed by bottom two layers. Note that if $\operatorname{Var}(f)=(d_{1},\ldots,d_{n})$, then $f$ can have at most $\prod(1+d_{i})$ monomials. Since $2^{x}\geq 1+x$ for all positive integers $x$, it follows that $\left|\operatorname{Var}(f)\right|\leq t$ implies that $f$ has at most $2^{t}$ monomials. Therefore, the total size of the $\Sigma\Pi\left(\Sigma\Pi\right)_{t}$ circuit is $2^{t}\cdot s^{O(kn/t)}=2^{O\left(t+\frac{kn\log s}{t}\right)}$. ∎

From Theorem 5.1 and setting $t=\sqrt{kn\log s}$ in 6.1, we get Theorem 1.7 restated below.

See 1.7

6.1 Reduction to higher depths

We now prove Theorem 1.8 which shows that similar savings can be obtained in depth reductions to larger depth.

See 1.8

Proof of Theorem 1.8.

We shall assume, without loss of generality, that the circuit $C$ is balanced (by applying Theorem 5.1 if necessary). The proof follows via repeated applications of 6.1.

Applying 6.1 with $t=nk/(nk/\log s)^{1/\Delta}$, we obtain a $\Sigma\Pi\left(\Sigma\Pi\right)_{t}$ circuit $C^{\prime}$ of the form

[TABLE]

with $s^{\prime}=s^{O\left((kn/\log s)^{1/\Delta}\right)}$ and $\left|\operatorname{Var}(g_{ij})\right|\leq t$ for all $i,j$. Furthermore, since each $g_{ij}$ being a polynomial computed by a gate in $C$, they are computable by multi-$k$-ic circuits of size at most $s$. By induction, each $g_{ij}$ has a multi-$k$-ic $(\Sigma\Pi)^{\Delta-1}$ circuit of size at most

[TABLE]

Replacing each $g_{ij}$ by this circuit, we obtain a $(\Sigma\Pi)^{\Delta}$ circuit of size at most

[TABLE]

∎

7 Open problems

The most interesting question that comes out of this work is to prove a lower bound of $n^{\omega(\sqrt{n/\log n})}$ for syntactically multilinear circuits of depth-$4$ for an explicit polynomial. A natural and first approach to this could be to understand if the shifted partials based methods can prove a lower a lower bound of $n^{\Omega(\sqrt{d})}$ for homogeneous depth-$4$ circuits for a polynomial family with degree $d=\omega(n/\log n)$.

Another question of interest would be to understand the correct exponent for the depth reduction results to depth-$4$ (and also to higher depth) for various regimes of the degree $d$. From [KS17], we know that for $d=O(n^{\varepsilon})$ for a small enough constant $\varepsilon$, $\sqrt{d}$ is the correct exponent, whereas for $d$ being nearly $n$, the results in this paper and those of Raz and Yehudayoff [RY09] show that the correct exponent is $\sqrt{n/\log n}$. But we do not understand this phenomenon for other values of $d$.

Acknowledgements

We are deeply thankful to Ben Rossman, who pointed us towards this question, and for many stimulating discussions at various stages of this work. We also thank Shubhangi Saraf, Amir Shpilka and Ben Lee Volk for many helpful conversations.

Mrinal is also thankful to Prahladh Harsha for accommodating him in his apartment for a part of the visit to TIFR, where a part of this paper was written.