# SPINBIS: Spintronics based Bayesian Inference System with Stochastic Computing

## TL;DR

SPINBIS introduces a spintronics-based stochastic computing system that significantly enhances the efficiency of Bayesian inference, leveraging device stochasticity and shared bitstream generation to outperform traditional approaches in energy and area metrics.

## Contribution

This work presents a novel spintronics-based stochastic computing architecture for Bayesian inference, including a shared bitstream generator strategy and a comprehensive performance evaluation framework.

## Key findings

- SPINBIS achieves 12x energy efficiency over MTJ-based methods.
- SPINBIS reduces design area overhead by 45%.
- SPINBIS is 26x more energy-efficient than FPGA-based systems.

## Abstract

Bayesian inference is an effective approach for solving statistical learning problems, especially with uncertainty and incompleteness. However, Bayesian inference is a computing-intensive task whose efficiency is physically limited by the bottlenecks of conventional computing platforms. In this work, a spintronics based stochastic computing approach is proposed for efficient Bayesian inference. The inherent stochastic switching behaviors of spintronic devices are exploited to build stochastic bitstream generator (SBG) for stochastic computing with hybrid CMOS/MTJ circuits design. Aiming to improve the inference efficiency, an SBG sharing strategy is leveraged to reduce the required SBG array scale by integrating a switch network between SBG array and stochastic computing logic. A device-to-architecture level framework is proposed to evaluate the performance of spintronics based Bayesian inference system (SPINBIS). Experimental results on data fusion applications have shown that SPINBIS could improve the energy efficiency about 12X than MTJ-based approach with 45% design area overhead and about 26X than FPGA-based approach.