Applicability of Partial Ternary Full Adder in Ternary Arithmetic Units

TL;DR

This paper demonstrates that complete ternary full adders are unnecessary for certain arithmetic units and introduces partial ternary full adders and compressors to simplify circuit design.

Contribution

It shows that partial ternary full adders suffice for key arithmetic units and proposes new ternary compressors, reducing circuit complexity.

Findings

Complete ternary full adders are not required in adder, subtractor, and multiplier units.

Partial ternary full adders can replace complete ones, simplifying circuit design.

New ternary compressors are proposed without needing complete ternary full adders.

Abstract

This paper explores whether or not a complete ternary full adder, whose input variables can independently be '0', '1', or '2', is indispensable in the arithmetic blocks of adder, subtractor, and multiplier. Our investigations show that none of the mentioned arithmetic units require a complete ternary full adder. Instead, they can be designed by use of partial ternary full adder, whose input carry never becomes '2'. Furthermore, some new ternary compressors are proposed in this paper without the requirement of complete ternary full adder. The usage of partial ternary full adder can help circuit designers to simplify their designs, especially in transistor level.