ENBB Processor: Towards the ExaScale Numerical Brain Box [Position Paper]

TL;DR

This paper proposes a novel microprocessor architecture inspired by brain topology, designed for exascale floating-point computations, emphasizing event-driven programming, a brain-like interconnection network, and virtual dataflows to improve efficiency.

Contribution

It introduces a new microprocessor concept with a brain-inspired topology, combining event-driven programming and virtual dataflows for exascale floating-point processing.

Findings

Design concept integrates brain topology with floating-point processing

Hypothesizes reduced memory needs through virtual interconnections

Proposes microprocessors with embedded main memory in 3D chips

Abstract

ExaScale systems will be a key driver for simulations that are essential for advance of science and economic growth. We aim to present a new concept of microprocessor for floating-point computations useful for being a basic building block of ExaScale systems and beyond. The proposed microprocessor architecture has a frontend for programming interface based on the concept of event-driven simulation. The user program is executed as an event-driven simulation using a hardware/software co-designed simulator. This is the flexible part of the system. The back-end exploits the concept of uniform topology as in a brain: a massive packet switched interconnection network with flit credit-based flow control with virtual channels that incorporates seamlessly communication, arithmetic and storage. Floating-point computations are incorporated as on-line arithmetic operators in the output ports of the switches as virtual arithmetic output channels, and storage as virtual input channels. The front-end carries out the event-driven simulation of the user program, and uses the arithmetic network for the hard floating-point work by means of virtual dataflows. We expect to reduce significantly the needs of main memory due to the execution model proposed, where variables are just virtual interconnections in the network or signals stored in the virtual channels. Moreover, we have the hypothesis that the problem size assigned to a microprocessor should allow maximum concurrency and it should not be oversized. This may lead to systems composed of microprocessors with main memory incorporated in 3D chips. We identified several challenges that a research to develop this microprocessor should address, and several hypothesis that should be demonstrated by means of scientific evidence.