A Reed Muller-based approach for optimization of general binary quantum multiplexers
Kevin Jin, Tahsin Saffat, Marek Perkowski

TL;DR
This paper introduces Reed-Muller-inspired forms for optimizing quantum multiplexers, significantly reducing gate costs for arbitrary target unitaries compared to previous non-minimal decompositions.
Contribution
It proposes fixed polarity and Kronecker quantum forms inspired by classical Reed-Muller forms, enabling efficient optimization of quantum multiplexers for arbitrary unitaries.
Findings
FPQF and KQF forms reduce gate cost in quantum multiplexers
Experimental results show significant optimization for various target gates
New forms outperform traditional methods in both random and benchmark data
Abstract
Previous work has provided methods for decomposing unitary matrices to series of quantum multiplexers, but the multiplexers created in this way are highly non-minimal. This paper presents a new approach for optimizing quantum multiplexers with arbitrary single-qubit quantum target functions. For quantum multiplexers, we define standard forms and two types of new forms: fixed polarity quantum forms (FPQF) and Kronecker quantum forms (KQF), which are analogous to Minterm Sum of Products forms, Fixed Polarity Reed-Muller (FPRM) forms, and Kronecker Reed-Muller (KRM) forms, respectively, for classical logic functions. Drawing inspiration from the usage of butterfly diagrams for FPRM and KRM forms, we devise a method to exhaustively construct all FPQF and KQF forms. Thus, the new forms can be used to optimize quantum circuits with arbitrary target unitary matrices, rather than only…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum-Dot Cellular Automata · Low-power high-performance VLSI design
