FPGA-Embedded Linearized Bregman Iterations Algorithm for Trend Break Detection

TL;DR

This paper presents a hardware implementation of the Linearized Bregman Iterations algorithm on FPGA for efficient trend break detection, achieving significant processing speed improvements over software versions.

Contribution

It introduces a novel FPGA-based hardware architecture for the Linearized Bregman Iterations algorithm, enhancing speed and efficiency in trend break detection tasks.

Findings

Approximately 100x faster processing time compared to software implementation

Effective hardware utilization across different FPGA sizes

High maximum frequency achieved by the hardware design

Abstract

Detection of level shifts in a noisy signal, or trend break detection, is a problem that appears in several research fields, from biophysics to optics and economics. Although many algorithms have been developed to deal with such problem, accurate and low-complexity trend break detection is still an active topic of research. The linearized Bregman Iterations have been recently presented as a low-complexity and computationally-efficient algorithm to tackle this problem, with a formidable structure that could benefit immensely from hardware implementation. In this work, a hardware architecture of the Linearized Bregman Iterations algorithm is presented and tested on a Field Programmable Gate Array (FPGA). The hardware is synthesized in different sized FPGAs and the percentage of used hardware as well as the maximum frequency enabled by the design indicate that an approximately 100 gain factor in processing time, with respect to the software implementation, can be achieved. This represents a tremendous advantage in using a dedicated unit for trend break detection applications.