# Protect Your Chip Design Intellectual Property: An Overview

## TL;DR

This paper reviews various techniques for protecting integrated circuit design intellectual property against threats like piracy, overproduction, and hardware Trojans, focusing on logic locking, layout camouflaging, and split manufacturing.

## Contribution

It provides a comprehensive overview of existing IP protection methods, their evolution, limitations, and future research directions.

## Key findings

- Logic locking and layout camouflaging are effective but have limitations.
- Split manufacturing offers additional security but faces practical challenges.
- Future work should address technique robustness and integration.

## Abstract

The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work.