# Static and Dynamic Oxide-Trapped-Charge-Induced Variability in Nanoscale CMOS Circuits

## TL;DR

This paper investigates static and dynamic variability in nanoscale CMOS circuits caused by oxide charge trapping and de-trapping, highlighting potential reliability issues due to single defect instabilities in ultrascale devices.

## Contribution

It presents a unified analysis of static and dynamic variability due to oxide charge trapping, supported by benchmarking on radiation-induced mismatch in 60 nm ICs.

## Key findings

- Oxide charge trapping causes both static and dynamic variability in nanoscale CMOS.
- Radiation increases inter-transistor mismatch in 60 nm ICs.
- Single charged defects can limit reliability in ultrascale circuits.

## Abstract

The inter-device mismatch and intra-device temporal instability in the nanoscale CMOS circuits is examined from a unified point of view as a static and dynamic parts of the variability con-cerned with stochastic oxide charge trapping and de-trapping. This approach has been benchmarked on the recent evidence of the radiation-induced increase of inter-transistor mismatch in 60 nm ICs. A possible reliability limitation in ultrascale circuits concerned with the single or a few charged defect instability is pointed out and estimated.

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Source: https://tomesphere.com/paper/1902.04974