Enhancing Fault Tolerance of Neural Networks for Security-Critical Applications

TL;DR

This paper proposes a revised neural network implementation that significantly enhances partial fault tolerance, crucial for security-critical applications like cryptography, demonstrated through software and FPGA evaluations on AES SBox.

Contribution

A novel methodology to improve the partial fault tolerance of neural networks with detailed mathematical analysis and practical FPGA and software evaluations.

Findings

Enhanced PFT significantly achieved with the proposed method

Successful FPGA and software implementation on AES SBox

Potential for safer neural network deployment in security-critical systems

Abstract

Neural Networks (NN) have recently emerged as backbone of several sensitive applications like automobile, medical image, security, etc. NNs inherently offer Partial Fault Tolerance (PFT) in their architecture; however, the biased PFT of NNs can lead to severe consequences in applications like cryptography and security critical scenarios. In this paper, we propose a revised implementation which enhances the PFT property of NN significantly with detailed mathematical analysis. We evaluated the performance of revised NN considering both software and FPGA implementation for a cryptographic primitive like AES SBox. The results show that the PFT of NNs can be significantly increased with the proposed methodology.