Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications

TL;DR

This paper introduces a workflow for designing FPGA-based accelerators for mobile deep learning applications, simplifying development with high-level synthesis tools and providing performance estimation models.

Contribution

It presents a novel workflow and an HLS-driven analytical model for efficient FPGA accelerator design targeting mobile deep learning tasks.

Findings

Accelerator design for low-power FPGA devices is feasible with the proposed workflow.

The analytical model effectively estimates performance and guides design improvements.

The approach enables faster development of mobile-friendly CNN accelerators.

Abstract

Recently, the field of deep learning has received great attention by the scientific community and it is used to provide improved solutions to many computer vision problems. Convolutional neural networks (CNNs) have been successfully used to attack problems such as object recognition, object detection, semantic segmentation, and scene understanding. The rapid development of deep learning goes hand by hand with the adaptation of GPUs for accelerating its processes, such as network training and inference. Even though FPGA design exists long before the use of GPUs for accelerating computations and despite the fact that high-level synthesis (HLS) tools are getting more attractive, the adaptation of FPGAs for deep learning research and application development is poor due to the requirement of hardware design related expertise. This work presents a workflow for deep learning mobile application acceleration on small low-cost low-power FPGA devices using HLS tools. This workflow eases the design of an improved version of the SqueezeJet accelerator used for the speedup of mobile-friendly low-parameter ImageNet class CNNs, such as the SqueezeNet v1.1 and the ZynqNet. Additionally, the workflow includes the development of an HLS-driven analytical model which is used for performance estimation of the accelerator. This model can be also used to direct the design process and lead to future design improvements and optimizations.