# Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS {\pi}-Junctions

## TL;DR

This paper introduces a new planarized fabrication process for superconductor electronics that integrates two layers of Josephson junctions, including SIS and SFS types, on 200-mm wafers, enabling more compact and functional superconductor circuits.

## Contribution

The paper presents a novel multilayer fabrication process that integrates SIS and SFS Josephson junctions in a fully planarized multilayer structure, enhancing circuit density and functionality.

## Key findings

- Successful integration of two junction layers with different J_c values.
- Demonstration of fabrication and characterization of both SIS and { extpi}-junctions.
- Process compatibility with 200-mm wafer production.

## Abstract

We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nb junctions with the same or different Josephson critical current densities, J_c. The process also allows integration of high-J_c Superconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junction layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact {\pi}-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target Josephson critical current densities for the SIS junctions are 100 {\mu}A/{\mu}m^2 and 200 {\mu}A/{\mu}m^2. We present the salient features of the new process, fabrication details, and characterization results on two layers of Josephson junctions integrated into one process, both for the conventional and {\pi}-junctions.

---
Source: https://tomesphere.com/paper/1902.02830