# Hybrid Cell Assignment and Sizing for Power, Area, Delay Product Optimization of SRAM Arrays

## TL;DR

This paper introduces a hybrid cell assignment and sizing approach for SRAM arrays that significantly reduces power, area, and delay costs, enhancing overall memory efficiency in digital systems.

## Contribution

It presents a novel hybrid cell assignment method using multi-sized and dual-Vth SRAM cells, combined with cell sizing techniques to optimize PAD in SRAM arrays.

## Key findings

- Achieved 34% improvement in PAD cost with hybrid cell assignment.
- Lowered PAD by up to 41% using combined assignment and sizing methods.
- Validated results in 32nm technology demonstrating significant efficiency gains.

## Abstract

Memory accounts for a considerable portion of the total power budget and area of digital systems. Furthermore, it is typically the performance bottleneck of the processing units. Therefore, it is critical to optimize the memory with respect to the product of power, area, and delay (PAD). We propose a hybrid cell assignment method based on multi-sized and dual-Vth SRAM cells which improves the PAD cost function by 34% compared to the conventional cell assignment. We also utilize the sizing of SRAM cells for minimizing the Data Retention Voltage (DRV), and voltages for the read and write operations in the SRAM array. Experimental results in a 32nm technology show that combining the proposed hybrid cell assignment and the cell sizing methods can lower PAD by up to 41% when compared to the conventional cell design and assignment.