A Low-Power 20-Gb/s Discrete-Time Analog Front-End for ADC-Based Serial Link Equalizers

TL;DR

This paper introduces a low-power, high-speed discrete-time analog frontend with a 4-bit charge-steering ADC for 20-Gb/s serial links, achieving efficient equalization and sampling in 65-nm CMOS.

Contribution

It presents a novel discrete-time linear equalizer combined with a low-power charge-steering ADC, enabling high-speed data conversion with minimal power consumption.

Findings

Total power dissipation is 17.78 mW at 20 GS/s.

ADC achieves an SNDR of 23.9 dB and ENOB of 3.67 bits.

The system operates effectively at 20 Gb/s in 65-nm CMOS.

Abstract

This paper presents a discrete-time analog frontend for an analog-to-digital (ADC) based equalizers. The frontend uses a discrete-time linear equalizer (DTLE) and ultralow-power 4-bit time-interleaved charge-steering flash ADC. The DTLE serves two functions; linear equalization and sampling and holding for the following charge-steering ADC. The ADC uses fully differential low-power clocked comparators. Low power in the comparators is achieved by embedding a dynamic latch into the core of a charge-steering pre-amplifier. The 20-Gb/s front-end is designed and simulated in 65-nm CMOS technology. The flash ADC uses 4-stage interleaving and thus requires 4 DTLEs running at 5 Gb/s. A 5-Gb/s DTLE consumes 0.57 mW from a 1.2-V supply and the ADC consumes 15.5 mW from a 1-V supply at 20 GS/s for a total power dissipation of 17.78 mW or 0.89 pJ/bit. The ADC has an SNDR of 23.9 dB, an SFDR of 33.6 dB, and an effective number of bits (ENOB) of 3.67 bits for a sinusoidal input of frequency 9.84 GHz and amplitude 600 mVdiff .

Figures

Equations

$${\omega }_z=\frac{1}{R_s{C}_s}$$

$${\omega }_{p1}=\frac{1+(g_m+g_{mb})R_s/2}{R_s{C}_s}$$

$${\omega }_{p2}=\frac{1}{R_d{C}_{pL}}$$

$$R_d=\frac{1}{{\mu }_p{C}_{ox}(W/L)(|V_{GS}|-|V_{th}|)}$$

$$Gai{n}_{DC}=\frac{(g_m+g_{mb})R_d}{1+(g_m+g_{mb})R_s/2}$$

$$Gai{n}_{Hi-freq}=g_m{R}_d$$

$$V_{out}=g_{m,avg}{R}_{out}{V}_{in}$$

$$\Delta T=\frac{C_T}{K}\frac{V_{CM}-V_{TH}-\Delta V}{(V_{CM}-V_{TH})\Delta V}$$

$$V_{out}=2\times \frac{V_{CM}-V_{TH}-\Delta V}{V_{CM}-V_{TH}+\Delta V}\times \frac{C_T}{C_{pL}}\times V_{in}$$

$$t_{delay}=t_0+t_{latch}$$

$$t_0=\frac{T_s}{4}$$

$$t_{latch}=\frac{C_{pL}}{g_{m,eff}}.ln(\frac{\Delta V_{out}}{\Delta V_{initial}})=\frac{C_{pL}}{g_{m,eff}}.ln(\frac{V_{DD}/2}{\Delta V_{initial}})$$

Full text

II Introduction

High-speed comparators with low-power consumption and small sensitivity are essential blocks in many applications that require very high sampling rates and low resolution such as data-storage read channels and wired communication systems [LABEL:paper:1]. As the demand for high rates increases, comparators must cope with this need while achieving as low power consumption and small area as possible. For example, recent communication links try to use ADC-based receivers which mainly depend on analog-to-digital converters (ADCs). However, power consumption remains a concern. A comparator is the main building block in any ADC. Improving its performance by reducing its kick-back noise and power consumption while maintaining high sampling rate will directly improve the whole ADC. As a result, the multi-standard reconfigurable systems which heavily depend on an ADC near the front end and digital blocks at the back end are becoming more common.

Time-interleaving has been widely used to allow for higher speed ADCs while keeping power consumption at reasonable levels. The power consumption overhead of interleaving becomes insignificant above certain frequencies when compared to the increase of the power consumption of a single-channel ADC.

The goal of the paper is to propose and analyze a novel topology, based on the charge-steering concept, for an ultra-low-power ultra-high-speed comparator. Then this comparator is used to build a low-power flash ADC to be used in a high-speed serial link ADC-based equalizer. A 4-bit 20-GS/s 4x time-interleaved flash ADC is used. Usually, serial link equalizers need some linear equalization to compensate for precursor inter-symbol interference (ISI), as a result, the design of the analog front-end of the equalizer is completed by adding discrete-time linear equalizer (DTLE) at the input.

The design of the DTLE is explained in section III. Section IV discusses the charge-steering concept. The proposed fully differential comparator is discussed in section V along with its proposed single-ended version and its delay analysis. Section VI shows the designed charge-steering Flash ADC based on that comparator. The simulation results of the comparator, the ADC, and its front-end are given in section VII. Finally, the work is concluded in section LABEL:sec:conc.

III Discrete-Time Linear Equalizer

Since the analog input is changing at very high speeds, Flash ADC-comparators might samples the input at different instances due to the different types of mismatches. To overcome this issue, a sample-and-hold (S/H) circuit is needed at the input of the ADC to make sure that the introduced input to all of the comparators is the same. During the reset mode of the comparators, the sample-and-hold circuit samples the input then hold it for the comparators during the amplification and the regeneration modes [LABEL:paper:Ismail_DTLE].

For pre-cursor ISI equalization, many designs adopted the conventional continuous-time linear equalizer (CTLE) [LABEL:paper:Gondi]. The main disadvantage of the CTLE is the direct and continuous path from supply to ground. That is why it is not a proper option for the low-power applications. A DTLE is a linear equalizer that replaces the conventional CTLE and its continuous-time nature to a discrete-time nature [LABEL:paper:Ismail_DTLE - LABEL:paper:Gondi]. It could be seen as a combined continuous-time linear equalizer and a sample-and-hold circuit.

The resistive loads in a conventional CTLE are replaced with switched resistors and the conventional current sources are replaced with clocked current sources as shown in Figure II. The circuit has two main modes of operation, the hold mode, and the track-and-equalize mode. When CLK signal is “High”, the track-and-equalize mode is activated. The clocked current sources and the loading resistors are “ON”, hence the DTLE works as a peaking amplifier as shown in Figure II (b). When CLK signal goes “Low”, the circuit enters the hold mode. The clocked current sources are “OFF” and the switched resistors are at high impedance and hence the output values are almost not changing during this phase as presented in Figure II (c). This is good for the ADC to follow and cancels the need for a sample-and-hold circuit. As a result, power is saved.

However, the input devices are not instantly switched off because some time is needed to charge the tails nodes to switch off the input devices, so the output nodes face some leakage and the amplitude drops a little. Some reset NMOS transistors $M7$ and $M8$ might be added to rapidly charge the tail nodes and thus switch off the input devices during the hold mode. This will decrease the leakage of the output node and solve the issue as shown in Figure III. The input at the end of the clock is sampled, processed and held.

The circuit is degenerated with a capacitor $C_{s}$ which is the main reason for the gain peaking. This capacitor with the degeneration resistor $R_{s}$ form a zero at $\omega_{z}$ and a pole $\omega_{p1}$, and these are added to the existing pole at the output node at $\omega_{p2}$. The locations of the poles and the zero are as following:

[TABLE]

[TABLE]

[TABLE]

where $R_{d}$ is the resistance of the clocked PMOS switch in the load that is kept in the linear region of operation.

[TABLE]

Some of the most important and meaningful quantities for the peaking amplifier is the DC gain, AC gain and the peaking it achieves. Peaking is defined as the ratio of the high-frequency gain to the low-frequency gain.

[TABLE]

[TABLE]

IV Charge-Steering Concept

Instead of using current-steering power-hungry circuits, discrete-time charge-steering circuits consume less power than their continuous-time current-steering counterparts, especially at high speeds. This advantage can be utilized in designing semi-analog circuits such as latches, demultiplexers, clock-and-data recovery (CDR) circuits, and comparators as well as mixed-mode systems such as ADCs [LABEL:paper:CS_razavi]. The main concept is converting the continuous-time current-steering circuit to a discrete-time charge-steering topology as in [LABEL:paper:CS_razavi]. The tail current source, as in Figure IV (a), is replaced with a charge source, and the load resistors with switched capacitors. Discrete-time operation requires two switches in the tail path and two at the output nodes as shown in Figure IV (b).

The operation of this charge-steering-based differential amplifier is divided into two phases; reset phase and amplification phase. In the reset phase, the tail capacitor is discharged while the output nodes are pre-charged to $V_{DD}$. In the amplification phase, the tail capacitor is connected to the tail node, drawing a current from the input pair while the outputs are disconnected from $V_{DD}$. Then, the input pair draws a differential current from the load capacitors in proportion to the differential input voltage. This results in an output voltage proportional to the input voltage. Figure IV was introduced in [LABEL:paper:CS_Feb2015] as a dynamic latch for digital signals utilizing charge-steering circuits. The extra back-to-back PMOS pair $M7$-$M8$ helps in extending the swing of the original amplifier. This circuit cannot be used as a comparator for analog signals. The reason is that for small input signals, the input pair $M1$-$M2$ is fighting against the regenerative latch $M7$-$M8$ and will need a long time constant to produce an output. Hence, at high clock frequencies, the sensitivity of this circuit is compromised.

V The Proposed Fully-Differential Comparator

The proposed comparator is utilizing the charge-steering concept as shown in Figure V. The basic charge-steering amplifier consists of transistors $M1$-$M6$, $M9$-$M12$ and two tail capacitors $C_{T}$ amplifies the input signal. In order to regenerate the output signal, a regenerative latch might be added after this stage which will cause an increase in the power consumption of the comparator drastically. In this proposed design, an idea of an embedded regenerative latch as in [LABEL:paper:embedded_latch] is used but it is turned “OFF” in the reset and amplification phases and is turned “ON” in the regeneration phase. This is achieved by switching the transistor $M13$ in Figure V. $M13$ isolates the regenerative latch from both reset and amplification phases in order to avoid fighting. This results in an ultra-fast amplification for very low power consumption. The role of the embedded regenerative latch is to redistribute the differential charge increasing the output voltage. A new clocking scheme is introduced to facilitate the proposed operation. Figure V shows the proposed clocking scheme. The operation is divided into three phases of operation: reset phase, amplification phase, and regeneration phase. Figure V shows the proposed circuit in its three phases of operation.

V-A Reset phase

This is the initial phase shown in Figure V (a). It initializes the circuit when CLK1 is low, CLK2 is high and CLK3 is high leading to $M5$ and $M6$ being “ON” and pre-charging the two output nodes to $V_{DD}$ such that $V_{out+}=V_{out-}=V_{DD}$. At the same time, $M9$ and $M10$ are “OFF” and the tail capacitors $C_{T}$ are discharged to GND through $M11$ and $M12$ resulting in $V_{C_{T}}=0$, where $V_{C_{T}}$ is the voltage across the tail capacitor.

V-B Amplification phase

In the second phase, CLK1 turns high and CLK2 turns low while CLK3 is still high leaving all nodes at a high impedance state as shown in Figure V (b). In this phase, the circuit acts like a differential amplifier typically as stated in section IV. The steady state of the differential output is proportional to the input voltage. The gain is mainly governed by $C_{T}$ and $C_{pL}$. Since there is no DC path to GND in this phase, the voltage difference is created by charge redistribution between the two output capacitors $C_{pL}$ and the tail capacitors $C_{T}$ while consuming little extra power consumption. At the end of this phase, the two output voltages are sitting at levels slightly higher than the voltage level $V_{min}$ as shown in Figure V. The output voltage difference is an amplified version of the input as explained before. The small-signal output voltage at the end of the amplification phase can be given by:

[TABLE]

Where $g_{m,avg}$ is the average transconductance of the input pair and $R_{out}$ is the effective resistance of the switched capacitor structure resulting from charging and discharging of the load capacitors $C_{pL}$: $R_{out}=\frac{\Delta T}{C_{pL}}$. Where $\Delta T$ is the discharging time of $C_{pL}$ which equals the charging time of the tail capacitor $C_{T}$ to make $V_{p}$ rises from zero to $V_{CM}-V_{TH}-\Delta V$ where $\Delta V$ is somewhat small and arbitrary voltage. $\Delta T$ is given in [LABEL:paper:book_razavi] as

[TABLE]

where K is a physical constant of transistor parameters.

The output voltage at the end of the amplification phase can be given by:

[TABLE]

V-C Regeneration phase

The third phase shown in Figure V (c) starts when CLK3 turns low. $M13$ turns ON, thus $M7$ and $M8$ form a cross-coupled regenerative latch with an initial condition given by the final value of the amplification phase. The differential output, hence, starts to grow exponential till it reaches its saturation limit where the upper limit is $V_{DD}$ and the lower limit is $V_{min}$. The cross-coupled devices work on regenerating the output voltage by charge redistribution between $C_{T}$, $C_{pL1}$ and $C_{pL2}$. Once one of the two outputs reaches $V_{DD}$ ($V_{out+}$), the regeneration operation stops and $M7$ turns “OFF” keeping ($V_{out-}$) sitting at a voltage $V_{min}$. The cross-coupled pair will prevent the lower output to be pulled high and hence preserves the regenerated output till the next reset phase.

On one hand, higher $C_{T}$ would lead to lower voltage levels after the charge-sharing operation taking place in the amplification phase. On the other hand, power consumption increases linearly with the $C_{T}$ value. In this design, a capacitance value of $30$ fF is chosen which resulted in an effective voltage gain at the end of amplification phase of 2.5 and a value of $V_{min}$ equal to 40% of the supply. This proposed architecture combines the pre-amplification and the regeneration functions of a typical comparator circuit into one stage. It also relies on the concept of charge redistribution and re-using the stored charges to obtain the required output voltage at the end of each phase. The comparator is sensitive to very small input voltages at extremely high speeds by enabling the regeneration after the amplification phase is done. The circuit consumes very low power consumption since there is no direct path from $V_{DD}$ to GND after the initial reset phase.

A single-ended version of the proposed comparator is shown in Figure V-D. This single-ended circuit works the same as the differential circuit with same timing scheme. A single-ended version can be used with a single-ended input where a clocked comparator is needed and will be used for comparison with the conventional strongARM comparator.

V-D Delay Analysis for the Proposed Circuit

According to the work published in [LABEL:ICM_paper_9], the total delay for the conventional StrongARM comparator is comprised of two time delays, $\mathit{t}_{0}$ and $\mathit{t}_{latch}$. In our proposed circuit. The delay $\mathit{t}_{0}$ represents the time taken in amplification phase which is the quarter of the clock cycle $\mathit{T}_{s}$. The delay $\mathit{t}_{latch}$ is the time taken by cross-coupled latch to regenerate outputs to distinct values. It is defined as the time taken to have a voltage difference at the output ($\Delta{V}_{out}$) equal to $V_{DD}/2$ starting from an initial output voltage difference $\Delta{V}_{initial}$ from equation 9. The total delay can be given as:

[TABLE]

[TABLE]

[TABLE]

Where $\mathit{g}_{m,eff}$ is the effective transconductance of the back to back PMOS pair.

VI Charge-Steering Flash ADC

Figure VI shows the flash ADC architecture. 4x interleaving is used while all four channels share the reference ladder to reduce the total power consumption. Four groups of 5 GHz clocks separated by $90^{o}$ phase shifts are used for the four channels. The proposed comparator is the main building block used in the ADC, it is followed by static RS latch to complete a flip-flop to successfully time the output with the clock edges. Sharing the reference ladder between the interleaved branches while keeping the kick-back noise at an acceptable level is also implemented and led to significant power reduction as well. The outputs of the four interleaved channels of Flash ADC were kept in thermometer code to be directly fed into digital signal processing (DSP) core for further digital feed-forward equalization (FFE) and/or decision-feedback equalization (DFE) according to the channel and link conditions. Moreover, This ADC can be used in a multi-standard system. It can be operated in a quarter-rate, a half-rate or a full-rate mode according to the required sampling rate. Noting that a DTLE circuit will replace the sample-and-hold circuit in each branch to equalize and sample and hold the input signal for each sub-ADC.

VI-A Sample-and-Hold Network

Since the analog input is changing at very high speeds, Flash ADC-comparators might samples the input at different instances due to the different types of mismatches. To understand this problem, consider a low-frequency input is introduced to the ADC, the input will almost have a constant amplitude while the array of comparators sampling it to make proper decisions. But with the case of a high-frequency input signal, its fast-varying nature and the mismatches between comparators, the input might be sampled at different instances by the different comparators and this will give wrong decisions across the comparators array.

An optional sample-and-hold circuit was designed at the beginning to buffer between input nodes and the comparators, thus isolating the input from the high input capacitance from the comparators bank. The input devices were found to have a small input capacitance and since the proposed comparator is dynamic, it already samples the input at an instance of time, so the sampling circuit is eliminated. For now, input signal could be directly fed to and sampled by the dynamic comparators banks. Usually, in ADC-based equalizers, a linear equalizer precedes the ADC. Using a discrete-time linear equalizer can merge the functions of both blocks together as explained in section III.

VI-B Clocking System and Buffers

For the proposed ADC, we need 3 clocks for each channel as in Figure V and hence we need 4 groups of these 3 clocks, each group is shifted by $90^{o}$ from the other. To get these 12 clocks, there are two main thoughts, a quadrature PI or using logic operations between shifted clocks. The latter method is functional but quite inaccurate. However, we adopted it for testing and checking functionality.

Figure VI-B presents the designed timing system used to provide our ADC with required 12 different clocks. A 10-GHz clock is provided from a higher level, it is introduced as a single-ended clock, this signal is buffered and inverted then injected into 2 CML latches. These 2 CML latches form together, with the shown connection, a divide-by-2 circuit. Since CML latches have non-rail-to-rail outputs, the outputs are fed into differential to single-ended CML to CMOS converters. The generated clock signals are buffered and used through NAND gates and other buffers to generate the whole 12 different clock signals. Buffers are used to be able to drive the comparators.

CML latch circuit was used to work properly with the input 10-GHz clock in a 65-nm technology. The differential to the single-ended converter with buffers are working as a CML to CMOS converter. Conventional CMOS NAND gates were adopted to generate the $75\%$ duty cycle clocks. The buffer chain was used to generate the $25\%$ duty cycle clocks as well and to drive the loads, the switches inside the comparators.

VII Simulation Results

The DTLE was simulated across a 12-inch FR4 channel, the model of the channel used is given in Figure VII. Data was transmitted through the channel with a 20-Gb/s rate and DTLE was running on 5-GHz clocks while consuming only 0.57 mW from a 1.2-V supply. The eye diagram at the end of the channel, i.e. input of the receiver, and the eye diagram after the DTLE are shown in Figure VII. The first eye diagram is totally closed, while the latter eye diagram has a vertical eye opening of 120 mV. Since the ADC has a differential dynamic range of 600 $mV_{pp}$ and a common-mode input voltage of 750 mV, the DTLE needs to be followed by a programmable gain amplifier (PGA) to match the DTLE output with the dynamic range and the input common-mode voltage of the ADC. In summary, Table VII compares the designed DTLE with the prior work in the literature.