Generic Connectivity-Based CGRA Mapping via Integer Linear Programming
Matthew J. P. Walker, Jason H. Anderson

TL;DR
This paper introduces a new ILP-based method for CGRA mapping that simplifies connectivity modeling, significantly reducing computation time while maintaining high accuracy, enabling practical mapping of complex architectures.
Contribution
It proposes deriving connectivity info from generic models to create simpler ILPs, improving speed without sacrificing much accuracy in CGRA mapping.
Findings
Speed-up of up to 37.6x over fully-generic ILP approach
All runtimes under 20 minutes, with 90th percentile at 410 seconds
Effective mapping across multiple CGRA architectures and benchmarks
Abstract
Coarse-grained reconfigurable architectures (CGRAs) are programmable logic devices with large coarse-grained ALU-like logic blocks, and multi-bit datapath-style routing. CGRAs often have relatively restricted data routing networks, so they attract CAD mapping tools that use exact methods, such as Integer Linear Programming (ILP). However, tools that target general architectures must use large constraint systems to fully describe an architecture's flexibility, resulting in lengthy run-times. In this paper, we propose to derive connectivity information from an otherwise generic device model, and use this to create simpler ILPs, which we combine in an iterative schedule and retain most of the exactness of a fully-generic ILP approach. This new approach has a speed-up geometric mean of 5.88x when considering benchmarks that do not hit a time-limit of 7.5 hours on the fully-generic ILP, and…
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