Meeting the Scaling Challenge for Post-Silicon Nanoelectronics using CaF2 Insulators

TL;DR

This paper demonstrates the use of crystalline CaF2 as a scalable, ultra-thin insulator for 2D MoS2 transistors, achieving low leakage and high performance, addressing key challenges in post-silicon nanoelectronics.

Contribution

It introduces CaF2 as a high-quality, epitaxial insulator compatible with 2D semiconductors, enabling scalable, ultra-thin gate dielectrics for nanoelectronic devices.

Findings

CaF2 forms a quasi van der Waals interface with 2D semiconductors.

Achieved sub-1 nm equivalent oxide thickness with low leakage.

Devices show record-small hysteresis and competitive performance.

Abstract

Two-dimensional (2D) semiconductors have been suggested both for ultimately-scaled field-effect transistors (FETs) and More-than-Moore nanoelectronics. However, these targets can not be reached without accompanying gate insulators which are scalable into the nanometer regime. Despite the considerable progress in the search for channel materials with high mobilities and decent bandgaps, finding high-quality insulators compatible with 2D technologies has remained a challenge. Typically used oxides (e.g. SiO2, Al2O3 and HfO2) are amorphous when scaled, while two-dimensional hBN exhibits excessive gate leakages. To overcome this bottleneck, we extend the natural stacking properties of 2D heterostructures to epitaxial fluorite (CaF2), which forms a quasi van der Waals interface with 2D semiconductors. We report scalable single-layer MoS2 FETs with a crystalline CaF2 insulator of about 2 nm thickness, which corresponds to an equivalent oxide thickness of less than 1 nm. While meeting the stringent requirements of low leakage currents, our devices exhibit highly competitive performance and record-small hysteresis. As such, our results present a breakthrough for very large scale integration towards commercially competitive nano-electronic devices.

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\alsoaffiliation

Ioffe Physical-Technical Institute, Polytechnicheskaya 26, 194021 St-Petersburg, Russia

Various two-dimensional (2D) semiconductors are now considered as channel materials in next-generation field-effect transistors (FETs), which are potentially suitable to extend the life of Moore’s law by enabling scaled channel geometries below 5 nm. For instance, several groups have reported FETs with graphene 1, silicene 2, black phosphorus 3, 4 and transition metal dichalcogenides, such as MoS2 5, 6, 7, 8, 9, MoSe2 10, MoTe2 11, WS2 12 and WSe2 13, 14. Excellent transistor characteristics have already been obtained for MoS2 FETs, such as on/off current ratios 7 up to 1010 and sub-threshold swing values down to 69 mV/dec 9. Furthermore, some attempts on circuit integration of MoS2 FETs have already been undertaken 15, 16.

However, one of the major research problems of 2D technologies is their miniaturization without considerable loss in already achieved device performance thresholds. While fabrication of competitive 2D FETs with scaled channel dimensions is already possible 17, scaling and precise control of the insulator thickness and quality remain a challenge. Typically, oxides known from Si technologies (e.g. SiO2, Al2O3 and HfO2) are used. These materials are amorphous when grown in thin layers, which makes the fabrication of high-quality interfaces with the channel difficult. In order to address this problem, different insulators have to be identified for next-generation 2D technologies. In particular, hexagonal boron nitride (hBN) has been intensively discussed in the literature 18. However, hBN has a small bandgap of about 6 eV 19, a small dielectric constant of 5.06 20, and unfortunate band offsets to most 2D materials. As scaled technologies require equivalent oxide thicknesses (EOT) below 1 nm (corresponding to a physical thickness of below 1.3 nm in hBN), hBN will result in excessive thermionic and tunneling leakage currents (see Supplementary Section 1). To overcome this bottleneck, we suggest here to use epitaxially grown (and thus crystalline) calcium fluoride (fluorite, CaF2) which has outstanding insulating properties even for a physical thickness of just about 2 nm (EOT of about 0.9 nm).

Epitaxially grown CaF2 is a high-k crystalline material with a very favourable combination of dielectric properties 21, such as a high dielectric constant ($\mathrm{\varepsilon}\,=\,$8.43), wide bandgap ($E_{\mathrm{g}}$ = 12.1 eV) and high effective carrier mass ($m^{*}$ = 1.0$m_{0}$). Also, its nearly perfectly matching lattice constant (0.546 nm) with Si (0.543 nm) and similarities between the fluorite and Si lattice structures allow growth of CaF2 layers on Si and Ge substrates using molecular-beam epitaxy (MBE) 22, 23 with very high quality. Furthermore, the CaF2(111) surface is terminated by F atoms, which makes it chemically inert and free of dangling bonds with H passivation 24 known to result in numerous reliability challenges. Owing to this, heteroepitaxy of 2D materials on the 3D CaF2 surface is possible even for considerable lattice mismatch 25, while leading to high-quality quasi van der Waals interface. In particular, recent studies have reported epitaxy of MoSe2 26 and MoTe2 27 on CaF2(111) bulk substrates. This further underlines that CaF2 is fully compatible with 2D semiconductors and thus can be considered an extremely promising insulating material for very large scale integration of 2D devices.

Note that CaF2 is only one material out of a wide class of epitaxial fluorides 22. Some of these materials (e.g. anti-ferromagnetic NiF2 28 and MnF2 29, diamagnetic ZrF2 29, ferroelectric BaMgF4 30) have additional fascinating properties which may revolutionize future electronic device technologies. Nevertheless, the real potential of fluorides in modern electronic devices is still not fully exploited. For instance, previously, CaF2 films have been mostly used as barrier layers in resonant tunneling diodes 31 and superlattices 32, together with CdF2 films. As for the use of CaF2 as a gate insulator in FETs, only a few working transistors with 640 nm thick CaF2 and poor reproducibility were reported 33. The considerable progress in MBE grown tunnel-thin CaF2 layers achieved in the last decade has revived the idea of fluoride insulators in FETs 34.

In this study we combine the epitaxial growth of CaF2 with chemical vapour deposition (CVD) of MoS2 in a single device. In order to study the variability and reproducibility of these devices, we fabricated hundreds of electrically stable single-layer MoS2 FETs with about 2 nm thick CaF2 gate insulators. Ultra-thin CaF2 layers were deposited onto an atomically clean Si(111) surface using our well-adjusted MBE growth technique 23 at 250oC (for more details see the Methods section). The growth process and crystalline quality of CaF2 were controlled in real time using reflection high-energy electron diffraction (RHEED) 35, the corresponding images are provided in Supplementary Section 2. The thickness of CaF2 measured by a quartz oscillator is 6 – 7  monolayers (ML, 1 ML = 0.315 nm), which is close to the values measured using transmission electron microscope (TEM). The first step of transistor fabrication consisted in formation of SiO2(5 – 10 nm)/Ti/Au source/drain contact pads using sputtering. Then, a single-layer MoS2 film grown by CVD 36 at 750oC was transferred onto the substrate according to the method of [37] (for more details see the Methods section) and MoS2 channels with $L$ and $W$ varied between 400 and 800 nm were shaped. Finally, additional e-beam evaporated Ti/Au layers were deposited to contact the channels. More details about the structure of our devices can be found in Supplementary Section 3.

In Fig. 1a we show that the atomic structure of CaF2(111) is rather similar to that of 2D materials, with F-Ca-F monolayers having a thickness of 0.315 nm. This makes fluorite a natural candidate for the integration into 2D process flows. An essential ingredient of our devices is the virtually defect-free CaF2(111)/MoS2 interface, which is formed by the F-terminated fluorite substrate, a quasi van der Waals gap and an atomically flat MoS2 layer (Fig. 1a). This interface is present in the channel area and under the source/drain electrodes, as marked in the scanning electron microscope (SEM) image in Fig. 1b. In order to verify the layer structure of our device, we cut a 70 nm thick specimen using focused ion beam (FIB) along the line marked in Fig. 1b and performed TEM measurements. In Fig. 1c we show a TEM image obtained for the channel area. We can clearly see the interface between single-layer MoS2 and layered crystalline CaF2 of about 8 ML, which corresponds to a physical thickness of about 2.5 nm. For different substrates, the number of CaF2 monolayers varies between 6 and 8 (thickness between 1.9 and 2.5 nm). By recording electron energy loss spectra (EELS, see Supplementary Section 5) at the interface between CaF2 and the Si substrate we observe some SiO2 (less than 1 nm thick), which is formed by oxidation resulting from prolonged exposure to air of our CaF2/Si substrates before device fabrication. Taking into account thickness fluctuations 23 of CaF2 and the presence of a thin thermal oxide layer, we model the tunnel leakages measured for numerous devices and find that the effective gate insulator thickness is about 2 nm (see Supplementary Section 4). The layered structure of our CaF2 films is clearly visible in the TEM image obtained using low dose imaging. Although electron irradiation is known to be destructive for CaF2 samples 38, these investigations indicate the extremely high stability of our thin CaF2 layers, where the desorption of F by the electron beam and subsequent formation of CaO are not as favourable as in CaF2 bulk crystals 38. Nevertheless, we found that TEM measurements can destroy the Si substrate a few nanometers below the Si/CaF2 interface, which, however, only occurs within the channel area (see Supplementary Section 5). Interestingly, outside the channel area our sample is unaffected by TEM irradiation. There we can clearly see MoS2 sandwiched between two metal layers and an SiO2 isolation layer on top of the CaF2/Si substrate (Fig. 1d,e). As a final verification of the properties of our 2 nm thick CaF2 insulator, in Fig. 1f we show that the measured gate leakage is negligible compared to the drain current of our MoS2 FET.

Using the process flow described above, we fabricated over 100 devices on two different CaF2 substrates. In Fig. 2a we show the gate transfer ($I_{\mathrm{D}}-V_{\mathrm{G}}$) characteristics measured for 50 devices from both substrates. The typical on-currents vary from 1 nA to nearly 10$\mu$A, which is likely because of the non-homogeneous nature of the CVD MoS2 film and different effective channel widths. At the same time, the measured on/off current ratios of some devices approach 107 (Fig. 2b), which is excellent for back-gated MoS2 FETs with a tunnel-thin gate insulator. Note that for the devices with overall lower currents, the measured on/off current ratios are probably underestimated due to the limited measurement resolution, which affects the off current. At the same time, the subthreshold swing (SS) values of most devices are smaller than 150 mV/dec, while being close to 90 mV/dec for some devices (Fig. 2b,c). These values are among the best ever reported for back-gated MoS2 FETs. Although in these prototypes SS$\,\sim\,$90 mV/dec is achieved mostly for the devices with lower current (Fig. 2c), several high-current devices also exhibit small SS values (e.g. Fig. 3). As such, we believe that further optimization of CVD MoS2 FETs on epitaxial fluorides and transition to more versatile configurations, such as top-gated devices and perhaps negative capacitance FETs with ferroelectric fluorides 30, will lead to further improvements of these emerging devices.

In Fig. 3a we show typical $I_{\mathrm{D}}-V_{\mathrm{G}}$ characteristics measured for a device which simultaneously exhibits high drain currents and steep SS. The best transistor performance is achieved at $V_{\mathrm{D}}\,=\,$1 V, with maximum measured on current about 5$\,\mu$A (or about 6$\,\mu$A/$\,\mu$m if normalized to the channel width), on/off current ratio close to 107 and SS as small as 93 mV/dec (Fig. 3b). The output ($I_{\mathrm{D}}-V_{\mathrm{D}}$) characteristics measured for different $V_{\mathrm{D}}$ (Fig. 3c) also show promising behaviour with a large degree of current control and saturation. All these results confirm the promising nature of our devices and thus the high potential for further development.

Finally, we verify the electrical stability of our MoS2/CaF2 FETs by performing ultra-slow sweep hysteresis measurements with total sweep times $t_{\mathrm{sw}}$ of several kiloseconds. In Fig. 4a we compare the $I_{\mathrm{D}}-V_{\mathrm{G}}$ characteristics measured for our MoS2/CaF2 devices with those of MoS2/SiO2 FETs with Al2O3 encapsulation reported in our previous work 7, which were found to exhibit the smallest hysteresis ever reported in 2D technologies. In addition to comparable values of $I_{\mathrm{D}}$ normalized to the channel width and considerably smaller SS for our MoS2/CaF2 FETs, we found that the hysteresis width near $V_{\mathrm{th}}$ is about 0.2 V in both cases. However, for a fair comparison these values need to be normalized to the insulator field factor $\Delta V_{\mathrm{G}}$/$d_{\mathrm{ins}}$ 7, with $\Delta V_{\mathrm{G}}$ being the width of $V_{\mathrm{G}}$ sweep range. While our devices with ultra-thin fluorite operate at considerably higher insulator fields of up to 15 MV/cm (against 6.4 MV/cm for the devices with thick SiO2), their hysteresis stability is even better than for encapsulated MoS2/SiO2 FETs and close to commercial Si/high-k FETs, not to mention less advanced devices (Fig. 4b). This confirms both the high electrical stability of CaF2 as a gate insulator and the reduced number of slow insulator traps near the CaF2/MoS2 interface. The latter indicates that in addition to an excellent transistor performance, 2D FETs with CaF2 are also more than competitive in terms of their reliability, which is a fundamental requirement for commercial applications.

In summary, we have reported single-layer CVD MoS2 FETs on an epitaxially grown CaF2 insulator of record small 2 nm thinness and demonstrated that our fully scalable technology allows fabrication of numerous transistors on a single chip. We have found that already these prototype devices can exhibit SS down to 90 mV/dec and on/off current ratios up to 107, which are among the best values ever reported for back-gated devices. Furthermore, we have demonstrated that our devices are of very high electrical stability even for insulator fields of 10 – 15 MV/cm and exhibit record small hysteresis ever measured for 2D devices. All this is due to the outstanding dielectric properties of CaF2 and its good compatibility with MoS2, which leads to a virtually defect-free quasi van der Waals interface between these materials. Together with the recent demonstration of epitaxial growth of 2D semiconductors on CaF2(111) 26, 27, our findings present a breakthrough towards enabling ultra-scaled dielectric layers for next-generation 2D nanoelectronics.

1 Methods

MBE growth of CaF2 insulators

Ultra-thin CaF2 layers were epitaxially grown on weakly doped single-crystal n-Si(111) substrates with $N_{\mathrm{D}}\,=\,10^{15}\,$cm*-3* and a misorientation of 5 to 10 angular minutes. Before the growth process, a protective oxide layer was formed after chemical treatment by following the procedure suggested by Shiraki 39. Then, this layer was removed by annealing for 2 minutes at 1200oC under ultra-high vacuum conditions ($\sim$10*-8*$-$10*-7* Pa). This allowed us to obtain an atomically clean 7$\times$7 Si(111) surface. After this, the CaF2 film was grown on this surface by MBE at 250oC, which is known to be the optimum temperature to produce pinhole-free homogeneous fluorite layers 23. The deposition rate of fluorite measured by a quartz oscillator was about 1.3 nm/min. The growth processes and crystalline quality of the CaF2 layers were monitored using RHEED with an electron energy of 15 keV (see the diffraction images shown in Supplementary Section 2).

Device fabrication

A single-layer MoS2 film serving as a channel was grown on c-plane sapphire using the CVD process described by Dumcenco et al 36. Namely, CVD growth was performed at atmospheric pressure and 750oC using sulfur and MoO3 as powder precursors and ultra-high-purity Ar as the carrier gas.

All lithography steps were done using E-Beam lithography. First we deposited SiO2(5–10 nm)/Ti/Au contact pads using sputtering. An isolation with the SiO2 layer is required to minimize parasitic leakage currents through the 15 – 20$\,\mathrm{\mu}$m sized square electrodes, which have to be so large for a reliable contact with the probe. Then 7$\times$7 mm CVD-grown MoS2 films were transferred onto the CaF2(111) substrate with pre-shaped isolated contact pads using the process suggested by Gurarslan et al 37. In particular, we used a polystyrene film as a carrier polymer and dissolved it in toluene after the transfer process. The transferred MoS2 film was subsequentily etched by reactive ion etching, in order to define the transistor channels with $L$ and $W$ between 400  and 800 nm. Finally, the channels were contacted by e-beam evaporated Ti/Au pads deposited on top of MoS2 in the contact areas. This second layer of Ti/Au was slightly extended to contact MoS2 on top of the bare CaF2 surface.

TEM measurements

In order to achieve a high contrast in TEM measurements, the devices were covered by a 10 nanometers thick carbon layer deposited using sputtering. After this a TEM lamella preparation process was performed with a dual beam system. First a thicker granular platinum protective layer was deposited using a focused electron beam followed by a focused ion beam deposition. Then a TEM lamella was cut out along the channel of the device. Finally, the samples were examined using a TEM setup at the pressure of about 10*-5* Pa. During the measurements, we recorded EELS spectra to verify the layer structure of our device.

Electrical characterization

Electrical characterization of our MoS2/CaF2 FETs consisted in the measurements of $I_{\mathrm{D}}-V_{\mathrm{G}}$ and $I_{\mathrm{D}}-V_{\mathrm{D}}$ characteristics. These measurements were conducted using a Keithley 2636 parameter analyzer in the chamber of a Lakeshore vacuum probestation ($\sim$5$\times$10*-6* torr) at room temperature and in complete darkness. In order to correctly resolve the on/off current ratio, we used the autorange measurement mode. The hysteresis of the $I_{\mathrm{D}}-V_{\mathrm{G}}$ characteristics was investigated by doing double sweeps with a constant sweep rate.

{acknowledgement}

The authors thank for the financial support through the Austrian Science Fund FWF grant n∘ I2606-N30. T.M., D.K.P. and S.W. acknowledge financial support by the Austrian Science Fund FWF (START Y 539-N16) and the European Union (grant agreement No. 785219 Graphene Flagship). This work was partly supported by the Russian Foundation for Basic Research (grant No. 18-57-80006 BRICS$\_$t). We also gratefully acknowledge useful discussions with Mr. Markus Jech. Y.Y.I. is a member of Mediterranean Institute of Fundamental Physics (MIFP).

2 Author contributions

Y.Y.I. introduced the idea of MoS2 FETs with ultra-thin CaF2 insulator, performed their characterization and prepared the manuscript. A.G.B. performed MBE growth of CaF2 and provided the substrates. D.K.P. and S.W. fabricated MoS2 FETs. M.S.-P. did TEM measurements. T.K. and M.T. contributed to preparation of figures. M.S-P. and A.S.-T. performed TEM measurements and sample preparation, respectively. M.I.V. performed quantitative analysis of gate leakage currents using tunnel models. M.W. programmed electrical measurements. N.S.S., T.M. and T.G. supervised this work. All authors regularly discussed the results and commented on the manuscript.