Tradeoff Between Delay and High SNR Capacity in Quantized MIMO Systems

TL;DR

This paper proposes a novel MIMO receiver architecture with delay elements that enhances high SNR capacity under low-resolution ADC constraints, revealing a tradeoff between delay and rate.

Contribution

It introduces a delay-based analog processing architecture that improves achievable rates in quantized MIMO systems, surpassing prior one-shot methods.

Findings

Achieves maximum transmission rate with fixed one-bit ADCs at high SNR.

Identifies a tradeoff between delay elements and achievable rate.

Demonstrates the benefit of blockwise analog combining over one-shot processing.

Abstract

Analog-to-digital converters (ADCs) are a major contributor to the power consumption of multiple-input multiple-output (MIMO) communication systems with large number of antennas. Use of low resolution ADCs has been proposed as a means to decrease power consumption in MIMO receivers. However, reducing the ADC resolution leads to performance loss in terms of achievable transmission rates. In order to mitigate the rate-loss, the receiver can perform analog processing of the received signals before quantization. Prior works consider one-shot analog processing where at each channel-use, analog linear combinations of the received signals are fed to a set of one-bit threshold ADCs. In this paper, a receiver architecture is proposed which uses a sequence of delay elements to allow for blockwise linear combining of the received analog signals. In the high signal to noise ratio regime, it is shown that the proposed architecture achieves the maximum achievable transmission rate given a fixed number of one-bit ADCs. Furthermore, a tradeoff between transmission rate and the number of delay elements is identified which quantifies the increase in maximum achievable rate as the number of delay elements is increased.

Figures

Equations

$$Y^{n_r}=h^{n_r\times n_t}{X}^{n_t}+N^{n_r},$$

$${\mathcal{F}}_a=\{f_a|f_a(Y^{n\times n_r})=(v^{n_q\times n_r}\otimes I_n){\tilde{Y}}^{n{n}_r}\},$$

$${\mathcal{B}}_{j_1,j_2,\cdots ,j_{n_q}}=\{y^{n_r}\in Im(h^{n_r\times n_t})|Q(w_i)=j_i,i\in [n_q]\}.$$

$$\underset{t^{n_q},v^{n_q\times n_r}}{\max }|\mathsf{B}(t^{n_q},v^{n_q\times n_r})-\{\varnothing \}|=\sum _{i=0}^{rank(h^{n_r\times n_t})}\left(\genfrac{}{}{0ex}{}{n_q}{i}\right).$$

$$\underset{v^{n_q\times n_r}}{\max }|\mathsf{B}(0^{n_q},v^{n_q\times n_r})-\{\varnothing \}|=2\sum _{i=0}^{rank(h^{n_r\times n_t})-1}\left(\genfrac{}{}{0ex}{}{n_q-1}{i}\right).$$

$${\tilde{Y}}^{\ell n_r}=(Y^{n_r}(1),Y^{n_r}(2),\cdots ,Y^{n_r}(\ell -1),Y^{n_r}(\ell )).$$

$${{\mathcal{F}}_a}^{\ell }=\{f_a|f_a(Y^{n\times n_r})=(v^{\ell n_q\times \ell n_r}\otimes I_b){\tilde{Y}}^{n{n}_r},b\in \mathbb{N}\},$$

$${\tilde{Y}}_{(j-2\ell )n_r+1}^{j{n}_r}=(Y^{n_r}(j-2\ell +1),Y^{n_r}(j-2\ell +2),\cdots ,Y^{n_r}(j-1),Y^{n_r}(j)),$$

$$C_{OS}(h^{n_r\times n_t},n_q)=C_1(h^{n_r\times n_t},n_q)\le C_{\ell }(h^{n_r\times n_t},n_q),$$

$$\frac{1}{2}\left(1-\sqrt{1-\frac{1}{3n}}\right)<\lambda <\frac{1}{2}\left(1+\sqrt{1-\frac{4}{12n+1}}\right),$$

$$\log \left(\genfrac{}{}{0ex}{}{n}{\lambda n}\right)=n{h}_b(\lambda )-\frac{1}{2}\log n-\frac{1}{2}\log 2\pi \lambda (1-\lambda )+O\left(\frac{1}{n}\right).$$

$$\log \sum _{i=0}^{\lambda n}\left(\genfrac{}{}{0ex}{}{n}{i}\right)=n{h}_b(\lambda )-\frac{1}{2}\log n-\frac{1}{2}\log \frac{2\pi \lambda (1-2\lambda {)}^2}{1-\lambda }+o\left(1\right).$$

$$n_q{h}_b(\alpha )-\frac{1}{2\ell }\log \ell -\frac{\text{mathbbm}{1}_{\{\alpha \ne \frac{1}{2}\}}}{2\ell }$$

$$\le n_q{h}_b(\beta )-\frac{1}{2\ell }\log \ell -\frac{\text{mathbbm}{1}_{\{\beta \ne \frac{1}{2}\}}}{2\ell }\log \frac{2\pi n_q\beta (1-2\beta {)}^2}{1-\beta }+o\left(\frac{1}{\ell }\right),$$

$$C_{\ell }\to n_q{h}_b(\beta )\text{ as }\ell \to \infty .$$

$$n_q{h}_b\left(\frac{rank(h^{n_r\times n_t})}{n_q}\right)=rank(h^{n_r\times n_t})(\log n_q-O(\log n_q)).$$

$$n!=\sqrt{2\pi n}{\left(\frac{n}{e}\right)}^n\left(1+\frac{1}{12n}+O\left(\frac{1}{n^2}\right)\right).$$

$$\left(\genfrac{}{}{0ex}{}{n}{n\lambda }\right)=\frac{n!}{(\lambda n)!((1-\lambda )n)!}$$

$$=\frac{\sqrt{2\pi n}{\left(\frac{n}{e}\right)}^n\left(1+\frac{1}{12n}+O\left(\frac{1}{n^2}\right)\right)}{\sqrt{2\pi \lambda n}{\left(\frac{\lambda n}{e}\right)}^{\lambda n}\left(1+\frac{1}{12\lambda n}+O\left(\frac{1}{(\lambda n{)}^2}\right)\right)\sqrt{2\pi (1-\lambda )n}{\left(\frac{(1-\lambda )n}{e}\right)}^{(1-\lambda )n}\left(1+\frac{1}{12(1-\lambda )n}+O\left(\frac{1}{((1-\lambda )n{)}^2}\right)\right)}$$

$$=\frac{1}{\sqrt{2\pi n\lambda (1-\lambda )}}\times \frac{1}{{\lambda }^{n\lambda }(1-\lambda {)}^{n(1-\lambda )}}\times \frac{1+\frac{1}{12n}+O\left(\frac{1}{n^2}\right)}{\left(1+\frac{1}{12n\lambda }+O\left(\frac{1}{n^2}\right)\right)\left(1+\frac{1}{12n(1-\lambda )}+O\left(\frac{1}{n^2}\right)\right)}$$

$$=\frac{1}{\sqrt{2\pi n\lambda (1-\lambda )}}\times \frac{1}{{\lambda }^{n\lambda }(1-\lambda {)}^{n(1-\lambda )}}\times \frac{1+\frac{1}{12n}+O\left(\frac{1}{n^2}\right)}{\left(1+\frac{1}{12n}\left(\frac{1}{1-\lambda }+\frac{1}{\lambda }\right)+O\left(\frac{1}{n^2}\right)\right)}$$

$$\stackrel{\text{(a)}}{=}\frac{1}{\sqrt{2\pi n\lambda (1-\lambda )}}\times \frac{1}{{\lambda }^{n\lambda }(1-\lambda {)}^{n(1-\lambda )}}\times \left(1+\frac{1}{12n}+O\left(\frac{1}{n^2}\right)\right)\left(1-\frac{1}{12n\lambda (1-\lambda )}+O\left(\frac{1}{n^2}\right)\right)$$

$$=\frac{1}{\sqrt{2\pi n\lambda (1-\lambda )}}\times \frac{1}{{\lambda }^{n\lambda }(1-\lambda {)}^{n(1-\lambda )}}\times \left(1+\frac{1}{12n}\frac{\lambda (1-\lambda )-1}{\lambda (1-\lambda )}+O\left(\frac{1}{n^2}\right)\right),$$

$$\log \left(\genfrac{}{}{0ex}{}{n}{n\lambda }\right)$$

$$=n{h}_b(\lambda )-\frac{1}{2}\log n-\frac{1}{2}\log 2\pi \lambda (1-\lambda )+O(1),$$

$$\left(\genfrac{}{}{0ex}{}{n}{\lambda n-j}\right)=\left(\genfrac{}{}{0ex}{}{n}{\lambda n}\right)\times \frac{\lambda n}{n-\lambda n+1}\times \frac{\lambda n-1}{n-\lambda n+2}\times \cdots \times \frac{\lambda n-j+1}{n-\lambda n+j},\lambda <\frac{1}{2},j\in [\lambda n].$$

$$\frac{\lambda n-i+1}{n-\lambda n+i}\le \frac{\lambda n}{n-\lambda n+i}<\frac{\lambda }{1-\lambda },i\in [\lambda n],$$

$$\frac{\lambda n-i+1}{n-\lambda n+i}\ge \frac{\lambda n-{\beta }_n+1}{n-\lambda n+{\beta }_n},\lambda n-{\beta }_n\le i\le \lambda n.$$

$$\sum _{i=0}^{\lambda n}\left(\genfrac{}{}{0ex}{}{n}{\lambda n-i}\right)\le \left(\genfrac{}{}{0ex}{}{n}{\lambda n}\right)\left(1+\frac{\lambda }{1-\lambda }+{\left(\frac{\lambda }{1-\lambda }\right)}^2+\cdots \right)=\left(\genfrac{}{}{0ex}{}{n}{\lambda n}\right)\frac{1-\lambda }{1-2\lambda }.$$

$$\sum _{i=0}^{\lambda n}\left(\genfrac{}{}{0ex}{}{n}{\lambda n-i}\right)\ge \sum _{i=0}^{\lambda n-{\beta }_n}\left(\genfrac{}{}{0ex}{}{n}{\lambda n}\right)\left(1+\frac{\lambda n-{\beta }_n+1}{n-\lambda n+{\beta }_n}+{\left(\frac{\lambda n-{\beta }_n+1}{n-\lambda n+{\beta }_n}\right)}^2+\cdots +{\left(\frac{\lambda n-{\beta }_n+1}{n-\lambda n+{\beta }_n}\right)}^{{\beta }_n}\right)$$

$$=\left(\genfrac{}{}{0ex}{}{n}{\lambda n}\right)\left(\frac{1-\lambda +\frac{{\beta }_n}{n}-(1-\lambda +\frac{{\beta }_n}{n})(\frac{\lambda n-{\beta }_n+1}{n-\lambda n+{\beta }_n}{)}^{{\beta }_n+1}}{1-2\lambda +\frac{1}{n}}\right).$$

$$\sum _{i=0}^{\lambda n}\left(\genfrac{}{}{0ex}{}{n}{\lambda n-i}\right)=\left(\genfrac{}{}{0ex}{}{n}{\lambda n}\right)\left(\frac{1-\lambda }{1-2\lambda }+o(1)\right).$$

$${\hat{x}}_{j^{\ell n_q}}^{\ell n_t}=argmi{n}_{{\hat{y}}_{j^{\ell n_q}}^{\ell n_r}=(h^{n_r\times n_t}\otimes I_{\ell })x^{\ell n_t}}\Vert x^{\ell n_t}{\Vert }_2,$$

$$c({\hat{y}}_{j^{\ell n_q}}^{\ell n_r})=mi{n}_{{\hat{y}}_{j^{\ell n_q}}^{\ell n_r}=(h^{n_r\times n_t}\otimes I_{\ell })x^{\ell n_t}}\Vert x^{\ell n_t}{\Vert }_2.$$

Full text

I Introduction

One of the most significant challenges in the development of 5G cellular communication technologies is energy consumption. The use of large antenna arrays leads to energy demands which are inconsistent with the limited power budget available in mobile devices and small-cell access points [1]. Analog to digital converters (ADCs) are a major contributor to the power consumption in multiple-input multiple-output (MIMO) receivers. In conventional MIMO systems with digital beamforming, it is assumed that each receiver antenna is connected to a high resolution ADC [2]. In standard ADC design, the power consumption is proportional to the number of quantization bins and hence grows exponentially in the number of output bits [3, 4]. One method which has been proposed to address high power consumption in MIMO systems with large number of antennas is to use low resolution ADCs (e.g. one-bit threshold ADCs) at each receiver antenna [5, 6, 7, 8, 9, 10, 11, 12]. Reducing the ADC resolution decreases power consumption, however, it also results in lower transmission rates. This suggests a tradeoff between transmission rate and power consumption which is controlled by the number and resolution of the ADCs at the receiver.

In classical information theory, it is well-known that in order to achieve optimal transmission rates, communication must be performed over asymptotically large blocks of data [13]. More precisely, an optimal decoder performs a possibly non-linear operation on an asymptotically large block of channel outputs. In MIMO systems using high resolution ADCs, the discretization loss is negligible due to the fine quantization grid. Simultaneous blockwise decoding is made possible by storing the digital output and performing the decoding operation over large blocklengths in the digital domain. However, when low resolution ADCs are used, discretizing the individual channel outputs prior to blockwise decoding leads to loss of information and suboptimal performance [6]. In particular, restricting to one-bit ADCs leads to large quantization noise, and a significant reduction in achievable rates [10, 8].

Rate-loss due to low resolution quantization can be attributed to two constituents which we call intrinsic and extrinsic rate-loss. To elaborate, consider the MIMO communication system shown in Fig. 1. Assume that the receiver is equipped with $n_{q}$ one-bit threshold ADCs. An upper-bound on the channel capacity is given by $\min(n_{q},C)$ bits per channel use, where $C$ is the capacity of the MIMO channel when using ADCs with very high resolution. In other words, due to the restriction on the number of ADCs, the channel capacity is decreased by at least $C-\min(n_{q},C)$ bits per channel-use. This intrinsic rate-loss cannot be reduced by improving the receiver architecture design without the use of additional one-bit ADCs. Considering the receiver architecture in Fig. 1(b), in practice only a limited set of analog operations illustrated as $f_{a}(\cdot)$ in the figure may be implemented. Prior works have studied the use of one-shot analog linear combiners and threshold ADCs [10, 8, 9, 11, 12]. It has been shown that the maximum rate achievable using the architecture in Fig. 1 is less than $\min(n_{q},C)$ due to practical limitations in analog processing [8]. More precisely, the communication system suffers an additional extrinsic rate-loss of $\min(n_{q},C)-R^{*}$ bits per channel-use, where $R^{*}$ is the maximum achievable rate when these practical limitations are taken into account. In theory, the extrinsic rate-loss may be reduced by improving the receiver architecture design.

In this work, we consider communication over MIMO channels where one-bit threshold ADCs are used at the receiver. We propose a blockwise analog processing module in which delay elements are used to reduce the extrinsic rate-loss due to one-bit ADCs. We show that for a large class of MIMO channels, in the high signal to noise ratio (SNR) regime, the proposed architecture completely eliminates the extrinsic rate-loss and achieves the maximum transmission rate among all receiver architectures with a fixed number of one-bit ADCs. We show the existence of a fundamental tradeoff between the number of delay elements and the maximum achievable rate for the proposed architecture. In addition, we show that given a fixed number of one-bit ADCs and delay elements, non-zero thresholds are necessary to achieve optimal transmission rates; whereas, using asymptotically large numbers of delay elements leads to optimal rates without requiring non-zero thresholds.

In the receiver architecture proposed in this paper, the ADC thresholds are chosen according to the channel gain matrix and are assumed to be fixed throughout the transmission block. In a companion paper [14], we propose a class of adaptive threshold receiver architecture, where the quantization thresholds at each channel-use are dependent on the channel outputs in the previous channel-uses. The fixed threshold architecture in this paper is simpler to implement. However, the adaptive threshold architecture in [14] is more amiable to analysis for point-to-point (PtP) communication in the low SNR regime and multiterminal communications.

The rest of the paper is organized as follows. Section II describes the system model. Section III includes the proposed receiver architecture along with an analysis of the resulting achievable rate region. Section IV concludes the paper.

Notation: the random variable $\mathbbm{1}_{\mathcal{E}}$ is the indicator function of the event $\mathcal{E}$. The set of numbers $\{1,2,\cdots,n\},n\in\mathbb{N}$ is represented by $[n]$. For a given $n\in\mathbb{N}$, the $n$-length vector $(x_{1},x_{2},\ldots,x_{n})$ is written as $x^{n}$. The subvector $(x_{k},x_{k+1},\cdots,x_{n})$ is denoted by $x_{k}^{n}$. We write $||x^{n}||_{2}$ to denote the $L_{2}$-norm of $x^{n}$. An $n\times m$ matrix is written as $h^{n\times m}=[h_{i,j}]_{i,j\in[n]\times[m]}$, and $[h^{n\times m}]^{\dagger}$ is the transpose of ${h^{n\times m}}$. Let $h^{n_{t}}_{(i)},i\in[m]$ be a sequence of column vectors; the notation $[h^{n}_{(1)},h^{n}_{(2)},\cdots,h^{n}_{(m)}]^{\dagger}$ represents the column vector of length $mn$ consisting of the concatenation of the original vectors. The $n\times n$ identity matrix is shown by $I_{n}$. We write $a^{n\times m}\otimes b^{n^{\prime}\times m^{\prime}}$ to denote the Kronecker product of matrices. The value of $i$ modulo $k$ is represented by $mod_{k}(i),i,k\in\mathbb{N}$. The binary entropy function is $h_{b}(x)=-x\log{x}-(1-x)\log(1-x)$.

II System Model and Preliminaries

II-A System Model

We consider a PtP communication system characterized by the triple $(n_{t},n_{r},h^{n_{r}\times n_{t}})$, where $n_{t}$ is the number of transmitter antennas, $n_{r}$ is the number of receiver antennas, and $h^{n_{r}\times n_{t}}$ is the channel gain matrix. The matrix $h^{n_{r}\times n_{t}}$ is assumed to be fixed over the transmission block, and known at the transmitter and receiver. The channel input and output vector pair $(X^{n_{t}},Y^{n_{r}})$ is related through

[TABLE]

where $N^{n_{r}}$ is a vector of independent and identically distributed Gaussian variables with unit variance and zero mean, and the channel input has average power constraint $P$. It is assumed that $n_{q}$ one-bit threshold ADCs are available at the receiver. The receiver uses the architecture shown in Fig. 1(b) which consists of an analog signal processing step prior to quantization and a digital signal processing step afterwards. The channel output is processed in the analog domain and the resulting vector is input to the ADCs. The output of the ADCs is processed in the digital domain to reconstruct the message. In its most general form, the analog processor may have causal memory. More precisely, the output of $f_{a}(\cdot)$ at time $i$, may depend on the matrix of received channel outputs $Y^{i\times n_{r}}$, where the $j$th row of $Y^{i\times n_{r}}$ is the channel output at time $j,j\leq i$. Let $n\in\mathbb{N}$ be the length of the transmission block and define $\mathcal{G}_{a}=\{f_{a}:\mathbb{R}^{n\times n_{r}}\to\mathbb{R}^{nn_{q}}\}$ as the space of all functions with causal memory. Due to practical considerations, only a subset of the functions in $\mathcal{G}_{a}$ are implementable. We denote the space of implementable functions by $\mathcal{F}_{a}$. The set of implementable functions $\mathcal{F}_{a}$ which are considered in this paper will be discussed in Section III. The communication problem is formalized below.

Definition 1** **(QMIMO).

A PtP MIMO system with one-bit ADCs (QMIMO) is characterized by the tuple $(n_{t},n_{r},h^{n_{r}\times n_{t}},n_{q},{\mathcal{F}_{a}})$, where $n_{q}$ is the number of one-bit ADCs, and ${\mathcal{F}_{a}}\subseteq\mathcal{G}_{a}$.

*Let $n,\Theta\in\mathbb{N}$ be a pair of natural numbers, $f_{a}\in{\mathcal{F}_{a}}$ an implementable analog function and ${t}^{nn_{q}}\in\mathbb{R}^{nn_{q}}$ a vector of quantization thresholds, where $t_{in_{q}-n_{q}+1}^{in_{q}},i\in[n]$ is the threshold vector in the $i$th channel use. An $(n,\Theta,f_{a},{t}^{nn_{q}})$-transmission system consists of a pair of encoding and decoding functions $(e,d)$ where $X^{n\times n_{t}}=e(M)$ is the channel input over $n$ channel uses and $\widehat{M}=d(Y^{n\times n_{r}})=f_{d}(Q^{nn_{q}}(f_{a}(Y^{n\times n_{r}})+{t}^{nn_{q}}))$ is the message reconstruction, $f_{d}:\{0,1\}^{nn_{q}}\to[\Theta]$ is a vector of Boolean functions, $Q^{nn_{q}}(x^{nn_{q}})=(\mathbbm{1}_{\{x_{1}\geq 0\}},\mathbbm{1}_{\{x_{2}\geq 0\}},\cdots,\mathbbm{1}_{\{x_{nn_{q}}\geq 0\}}),x^{nn_{q}}\in\mathbb{R}^{nn_{q}}$ is a sequence of one-bit ADCs. Achievability is defined in the standard Shannon sense. The capacity maximized over all implementable analog functions is denoted by $C_{Q}(h^{n_{r}\times n_{t}},n_{q},{\mathcal{F}_{a}})$. *

In [8], a receiver architecture is considered where the analog processing module consists of linear combiners along with non-zero threshold ADCs. The architecture is shown in Fig. 2. The linear combiner matrix $v^{n_{q}\times n_{r}}$ is applied to the received signals at each channel-use. This receiver architecture does not allow for temporal processing of the received signals in the analog domain. More precisely, the set $\mathcal{F}_{a}$ considered in [8] consists of all memoryless and linear analog processors:

[TABLE]

where $\widetilde{Y}_{kn+1}^{(k+1)n},k\in\{0,1,\cdots,n_{r}-1\}$ is equal to the $k$th row of $Y^{n\times n_{r}}$. We call this receiver architecture, one-shot. The channel capacity using this one-shot architecture maximized over all input distributions, threshold vectors, and linear combining matrices is denoted by $C_{OS}(h^{n_{r}\times n_{t}},n_{q})$.

It is known that one-shot processing of the analog signals leads to a significant extrinsic rate-loss [8, 10]. In fact, the one-shot capacity is shown to grow at most logarithmically in the number of one-bit ADCs. Consequently, in the high SNR regime, the extrinsic rate-loss due to the application of one-shot receiver architectures is at least111We write $f(x)=O(g(x))$ if $\lim_{x\to\infty}\frac{f(x)}{g(x)}<\infty$. $n_{q}-O(\log{n_{q}})$ and becomes arbitrarily large as the number of ADCs is increased.

In Section III, we introduce blockwise analog processing architectures which use delay elements to allow for temporal processing of the analog signals before quantization. We show in Theorem 1 that this allows us to completely eliminate the extrinsic rate-loss in a large class of MIMO systems in the high SNR regime including MIMO systems where the number of one-bit ADCs is at least twice the number of transmitter antennas and receiver antennas. To analyze the performance of the proposed architecture, we utilize a geometric interpretation introduced in [8, 10]. The geometric interpretation is especially helpful in analyzing the set of achievable rates in the high SNR regime.

The geometric interpretation and combinatorial background is briefly described in the next subsection.

II-B Combinatorial Background

Loosely speaking, as the SNR is increased, the effect of noise in Equation (1) becomes negligible and the channel output is almost equal to $h^{n_{r}\times n_{t}}X^{n_{t}}$. In fact, in the absence of noise, the channel output space is $Im(h^{n_{r}\times n_{t}})$ the image of the channel gain matrix $h^{n_{r}\times n_{t}}$. In the following, we describe the relation between partitions of the subspace $Im(h^{n_{r}\times n_{t}})$ and the maximum transmission rate when one-shot receiver architectures are used.

Consider the one-shot architecture described in Fig. 2. For a given channel output vector $y^{n_{r}}$, let $j_{i}=Q({w}_{i}),i\in[n_{q}]$, where ${w}^{n_{q}}=v^{n_{q}\times n_{r}}y^{n_{r}}+t^{n_{q}}$ is the input vector to the one-bit ADCs. The binary vector $j^{n_{q}}$ is the vector of ADC outputs. The set of all channel output vectors $y^{n_{r}}$ which result in the ADC output vector $j^{n_{q}}$ is

[TABLE]

For a given pair $(t^{n_{q}},v^{n_{q}\times n_{r}})$, the collection of sets $\mathsf{B}(t^{n_{q}},v^{n_{q}\times n_{r}})=\{\mathcal{B}_{j_{1},j_{2},\cdots,j_{n_{q}}}|j_{i}\in\{0,1\},i\in[n_{q}]\}$, is a partition of $Im(h^{n_{r}\times n_{t}})$. The number of non-empty partition elements corresponds to the number of messages which can be transmitted reliably as the SNR is taken to be asymptotically large. Note that for some binary vectors $j^{n_{q}}$, the set $\mathcal{B}_{j_{1},j_{2},\cdots,j_{n_{q}}}$ may be empty. For instance, let $n_{t}=n_{r}=1$, $n_{q}=2$, $h^{n_{r}\times n_{t}}=1$, $v^{n_{q}\times n_{t}}=\begin{bmatrix}1\\ 1\end{bmatrix}$, and $t^{n_{q}}=\begin{bmatrix}0\\ 0\end{bmatrix}$. Then $\mathcal{B}_{0,1}=\{y|Q(y)=0,Q(y)=1\}=\varnothing$, similarly, $\mathcal{B}_{1,0}=\varnothing$. As a result, the number of partition elements may be less than $2^{n_{q}}$. In order to increase the transmission rate, it is desirable to choose $(t^{n_{q}},v^{n_{q}\times n_{r}})$ such that the number of non-empty partition elements is maximized.

We use the following proposition throughout the paper.

Proposition 1**.**

*([15])

The maximum number of non-empty partition elements is given by*

[TABLE]

Additionally , if the threshold vector is taken to be the all-zero vector, then:

[TABLE]

The maximum number of non-empty partition regions grows exponentially in $n_{q}$ since $\log{{n\choose k}}=nh_{b}(\frac{k}{n})+O(\log{n})$ as shown in Proposition 2.

III Blockwise Receiver Architectures

We propose blockwise receiver architectures in which delay elements are used to perform blockwise temporal processing of the received signals before quantization. Communication is performed in $n=\ell b$ channel-uses, where $n$, $\ell$ and $b$ are called the blocklength, inner blocklength, and outer blocklength, respectively. The blockwise receiver architecture uses a delay network consisting of $2\ell$ delay elements as shown in Fig. 3, where each delay element $D_{n_{r}}(\cdot)$ takes the vector of received signals at the $i$th channel-use $Y^{n_{r}}(i)$ and outputs $Y^{n_{r}}(i-1)$. In other words, $D_{n_{r}}(\cdot)$ delays the received analog vector by one channel-use. The stored analog signals are combined using the linear combining matrix $v^{\ell n_{q}\times\ell n_{r}}$ over $\ell$ channel-uses.

To clarify the linear combination process, let us describe the first $3\ell$ channel-uses. In the first $\ell$ channel-uses the received signals $Y^{n_{r}}(i),i\in[\ell]$ are stored in the delay network. In the next $\ell$ channel-uses, the second batch of received signals $Y^{n_{r}}(i),\ell+1\leq i\leq 2\ell$ are stored in the delay network while the linear combiner operates on the previously stored signals $Y^{n_{r}}(i),i\in[\ell]$. More precisely, for the $i$th channel-use where $\ell+1\leq i\leq 2\ell$, the linear combiner outputs $\overline{Y}_{(i-\ell-1)n_{q}+1}^{(i-\ell)n_{q}}$, where $\overline{Y}^{\ell n_{q}}=v^{\ell n_{q}\times\ell n_{r}}\widetilde{Y}^{\ell n_{r}}$, and

[TABLE]

In the third $\ell$ channel-uses, the third batch of received signals $Y^{n_{r}}(i),2\ell+1\leq i\leq 3\ell$ are stored in the delay network while the linear combiner operates on the previously stored signals $Y^{n_{r}}(i),i\in[\ell]$. This process continues for $b$ blocks of length $\ell$ until the $n$th channel-use, where $n$ is the blocklength. The output of the linear combiner is given to the $n_{q}$ one-bit threshold ADCs. The threshold vector used in the one-bit ADCs changes periodically with a period of $\ell$ channel-uses. More precisely, let $t^{\ell n_{q}}\in\mathbb{R}^{\ell n_{q}}$ and define $\widetilde{t}^{n_{q}}(k)=t_{kn_{q}-n_{q}+1}^{kn_{q}},k\in[\ell]$. For the $\ell$ first channel-uses, the threshold vector $\widetilde{t}^{n_{q}}(i)$ is used in the $i$th channel-use. For the second $\ell$ channel-use, the threshold vector $\widetilde{t}^{n_{q}}(i-\ell)$ is used in the $i$th channel-use. Generally, for $i\in[n]$, let $k=mod_{\ell}(i)$, the vector $t^{n_{q}}(k)$ is used as the threshold vector for the one-bit ADCs at the $i$th channel-use.

We call the resulting communication system a D-QMIMO system, where $D$ refers to delay. The set of implementable analog functions for this architecture is:

[TABLE]

where

[TABLE]

where $2\ell\leq j\leq n$. The channel capacity optimized over all analog combining matrices, and threshold vectors is denoted by $C_{\ell}(h^{n_{r}\times n_{t}},n_{q})$ for a given delay $\ell$.

Note that D-QMIMO systems are a special class of QMIMO systems where the analog processing is restricted to linear operations. Furthermore, the one-shot setup described in Fig. 2 is a special case of D-QMIMO where the length of each inner-block is equal to one (i.e. $\ell=1$). As a result,

[TABLE]

where $\ell\geq 2$.

We derive the bounds provided in Theorem 1 below on the performance of the following proposed coding strategy. Consider a D-QMIMO communication system where $(t^{\ell n_{q}},v^{\ell n_{q}\times\ell n_{r}})$ are taken so that the partition $\mathsf{B}(t^{\ell n_{q}},v^{\ell n_{q}\times\ell n_{r}})$ has the maximum number of non-empty elements as described in Proposition 1. In other words, $(t^{\ell n_{q}},v^{\ell n_{q}\times\ell n_{r}})$ are chosen such that the number of non-empty partitions is equal to $\sum_{i=0}^{\ell rank(h^{n_{r}\times n_{t}})}{\ell n_{q}\choose i}$. We use the fact that $\log{{n\choose k}}=nh_{b}(\frac{k}{n})+O(\log{n})$ as shown in Proposition 2 and perform a second order analysis of the number of non-empty partition elements as the number of delay elements $\ell$ is increased asymptotically to characterize the set of achievable rates for high SNRs. We make use of the following proposition.

Proposition 2**.**

Let $n\in\mathbb{N}$ and $\lambda\in(0,1)$ such that

[TABLE]

Then, the following equality holds:

[TABLE]

Particularly, for asymptotically large $n$, Equation (5) holds for any fixed $\lambda\in(0,1)$. Furthermore, for $\lambda\in(0,\frac{1}{2})$, we have222We write $f(x)=o(g(x))$ if $\lim_{x\to\infty}\frac{f(x)}{g(x)}=0$.

[TABLE]

The proof is provided in the Appendix.

Theorem 1**.**

For the D-QMIMO communication system with $n_{q}$ one-bit ADCs, the capacity $C_{\ell}$ satisfies the following

[TABLE]

as SNR$\to\infty$, where $\alpha=\min\{\frac{rank(h^{n_{r}\times n_{t}})}{n_{q}},\frac{1}{2}\}$, $\beta=\min\{\frac{n_{r}}{n_{q}},\frac{1}{2}\}$. Particularly, if $rank(h^{n_{r}\times n_{t}})=n_{r}$, then

[TABLE]

The proof is provided in the Appendix, where a general coding strategy for arbitrary SNRs is presented. The resulting rate is analyzed in the high SNR regime.

The following observations follow from Theorem 1:

I) The capacity approaches $n_{q}$ as $\ell\to\infty$ if $n_{q}\leq 2rank(h^{n_{r}\times n_{t}})$. Consequently, the extrinsic rate-loss is completely eliminated. This is in contrast with prior works (e.g. [8], [10]), where the high SNR capacity grows logarithmically in $n_{q}$.

II) The maximum achievable rate due to using non-zero threshold ADCs is $\frac{1}{\ell}\log{\sum_{i=0}^{\ell rank(h^{n_{r}\times n_{t}})}{\ell n_{q}\choose i}}$, whereas when zero threshold ADCs are used, the maximum rate is $\frac{1}{\ell}\log{\sum_{i=0}^{\ell rank(h^{n_{r}\times n_{t}})-1}2{\ell n_{q}-1\choose i}}$. The two values converge to each other as $\ell\to\infty$. This shows that when long delays $\ell$ can be tolerated, zero threshold ADCs can be used in scenarios where non-zero thresholds are costly to implement without any loss in transmission rate.

**III) **For a fixed number of transmitters $n_{t}$ and receivers $n_{r}$, as the number of one-bit ADCs $n_{q}$ is increased, the maximum achievable rate increases linearly when $n_{q}\leq 2rank(h^{n_{r}\times n_{t}})$ since $h_{b}(\alpha)=h_{b}(\frac{1}{2})=1$. The maximum achievable rate increases logarithmically when $n_{q}\gg 2rank(h^{n_{r}\times n_{t}})$ since

[TABLE]

This is shown in Fig. 4, where for a MIMO system with $n_{r}=10$, the achievable rate in Theorem 1 is plotted as a function of $n_{q}$ for $n_{t}\in\{2,4,6,8\}$ as the number of delay elements is taken to be asymptotically large.

IV Conclusion

We have considered point-to-point communication over MIMO systems when a limited number of one-bit ADCs are available at the receiver. We have proposed a receiver architecture which uses a sequence of delay elements to allow for blockwise linear combining of the received analog signals. In the high SNR regime, given a fixed number of one-bit ADCs, we have shown that the proposed architecture achieves the maximum transmission rate among all receiver architectures. Furthermore, we have characterized a tradeoff between transmission rate and the number of delay elements which quantifies the increase in maximum achievable rate as the number of delay elements is increased. In a companion paper [14] we propose a class of adaptive threshold architectures analyze their performance in PtP communications in the low SNR regime and broadcast channel communications.

Proof of Proposition 2

From Stirling’s approximation, we have:

[TABLE]

Consequently, we have:

[TABLE]

where in (a) we have used the Taylor series expansion $\frac{1}{1+x}=1-x+O(x^{2}),x\in(-1,1)$. Note that Equation (4) ensures that $\frac{1}{12n}\left(\frac{1}{1-\lambda}+\frac{1}{\lambda}\right)\in(-1,1)$ holds. Consequently, we have:

[TABLE]

where in the last equality we have used the Taylor expansion $\ln{(1+x)}=1-x+O(x^{2}),x\in(-1,1]$ to conclude that $\left(1+\frac{1}{12n}\frac{\lambda(1-\lambda)-1}{\lambda(1-\lambda)}+O\left(\frac{1}{n^{2}}\right)\right)=-\frac{1}{2}\log{2\pi\lambda(1-\lambda)}+O(\frac{1}{n})$. Note that Equation (4) ensures that $\frac{1}{12n}\frac{\lambda(1-\lambda)-1}{\lambda(1-\lambda)}\in(-1,1]$ holds. This completes the proof of Equation (5).

Next, we prove Equation (6). Note that

[TABLE]

Let $\beta_{n}=n^{\epsilon}$, $\epsilon\ll 1$. We have:

[TABLE]

From Equations (7) and (8), we have:

[TABLE]

From equations (7) and (9), we have:

[TABLE]

Note that $(1-\lambda+\frac{\beta_{n}}{n})(\frac{\lambda n-\beta_{n}+1}{n-\lambda n+\beta_{n}})^{\beta_{n}+1}=o(1)$. Consequently, from using the Taylor series expansion of $\frac{1}{1+x},x\in(-1,1)$, we have:

[TABLE]

From Equations (10) and (11) we get

[TABLE]

This along with Equation (5) proves Equation (6).

Proof of Theorem 1

To prove the achievability (lower bound on $\mathcal{C}_{\ell}$), we describe an outline of the coding strategy for arbitrary SNRs, where the average transmission power constraint is $\mathbb{E}(||X^{n_{t}}||_{2})\leq P$. The resulting communication rate is analyzed as SNR$\to\infty$. Fix $\ell$ and $b$, where $b$ is the outer code blocklength.

Consider the pair $(t^{\ell n_{q}},v^{\ell n_{q}\times\ell n_{r}})$ which achieve the maximum number of non-empty sets in Proposition 1. For a given rate $R$, define $\Theta_{n}=2^{nR}$, where $n=b\ell$. The message $M\in[\Theta_{n}]$ is transmitted over $b+1$ transmission blocks each of $\ell$ symbols, where each symbol is in $\mathbb{R}^{n_{t}}$. Let $\mathsf{B}(t^{\ell n_{q}},v^{\ell n_{q}\times\ell n_{r}})=\{\mathcal{B}_{j^{\ell n_{q}}}|j_{i}\in\{0,1\},i\in[\ell n_{q}]\}$ be the partition corresponding to the pair $(v^{\ell n_{q}\times\ell n_{r}},t^{\ell n_{q}})$ as defined in Section II. Define $\mathcal{J}=\{j^{\ell n_{q}}\in\{0,1\}^{\ell n_{q}}|\mathcal{B}_{j^{n_{q}}}\neq\varnothing\}$, and let $\hat{y}^{\ell n_{r}}_{j^{\ell n_{q}}}\in\mathcal{B}_{j^{\ell n_{q}}},j^{\ell n_{q}}\in\mathcal{J}$ be a set of representatives for the partition elements. We define the input vector corresponding to $\hat{y}^{\ell n_{r}}_{j^{\ell n_{q}}}$ as

[TABLE]

and the cost associated with $\hat{y}^{\ell n_{r}}_{j^{\ell n_{q}}}$ as:

[TABLE]

We define the transition probability $P_{{Z}^{\ell n_{r}}|\widehat{Y}^{\ell n_{t}}}$ as:

[TABLE]

where $j^{\ell n_{q}},~{}k^{\ell n_{q}}\in\mathcal{J}$. Let ${C}_{outer}$ be the capacity of the PtP channel with the transition probability $P_{{Z}^{\ell n_{r}}|\widehat{Y}^{\ell n_{r}}}$ subject to the average power constraint $\mathbb{E}(c(\widehat{Y}^{\ell n_{r}}))\leq\ell P$. We first construct a family of capacity achieving codes for this channel using standard random coding methods. Each symbol $\widehat{Y}_{I^{\ell n_{q}}}^{\ell n_{r}}$ in the randomly generated codewords has alphabet $\mathbb{R}^{\ell n_{r}}$. In order to transmit the symbol $\widehat{Y}_{I^{\ell n_{q}}}^{\ell n_{r}}$, the transmitter finds the corresponding input $X^{\ell n_{t}}$ (Equation (12)) and transmits the vector over $\ell$ channel uses. As the SNR goes to infinity, the channel $P_{{Z}^{\ell n_{r}}|\widehat{Y}^{\ell n_{t}}}$ becomes noiseless. The resulting rate converges to

[TABLE]

This completes the proof of achievability. Next we prove the converse result. Using Fano’s inequality, it is straightforward show that $C_{\ell}\leq\frac{1}{\ell}\log{|\widehat{\mathcal{Y}}^{\ell n_{r}}|}$. Note that $|\widehat{\mathcal{Y}}^{\ell n_{r}}|$ is equal to the number of partition regions of the $\ell n_{r}$ dimensional Euclidean space. From Proposition 1, the maximum number of partitions is equal to ${\sum_{i=0}^{\ell n_{r}}{\ell n_{q}\choose i}}$. By the same arguments as in the achivability proof, it can be shown that:

[TABLE]