Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results
P Balasubramanian, D L Maskell, N E Mastorakis

TL;DR
This paper introduces an asynchronous early output block carry lookahead adder with redundant carries that significantly reduces latency and cycle time without increasing area or power consumption.
Contribution
It proposes a novel asynchronous BCLA with redundant carries and a hybrid BCLA-RCA variant, improving speed metrics over existing designs without additional area or power costs.
Findings
13% reduction in forward latency
14.8% reduction in cycle time
Additional 4% latency reduction with hybrid design
Abstract
A new asynchronous early output block carry lookahead adder (BCLA) incorporating redundant carries is proposed. Compared to the best of existing semi-custom asynchronous carry lookahead adders (CLAs) employing delay-insensitive data encoding and following a 4-phase handshaking, the proposed BCLA with redundant carries achieves 13% reduction in forward latency and 14.8% reduction in cycle time compared to the best of the existing CLAs featuring redundant carries with no area or power penalty. A hybrid variant involving a ripple carry adder (RCA) in the least significant stages i.e. BCLA-RCA is also considered that achieves a further 4% reduction in the forward latency and a 2.4% reduction in the cycle time compared to the proposed BCLA featuring redundant carries without area or power penalties.
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Taxonomy
TopicsAnalog and Mixed-Signal Circuit Design · Low-power high-performance VLSI design · Advancements in PLL and VCO Technologies
