# SVE-enabling Lattice QCD Codes

## TL;DR

This paper discusses optimizing lattice QCD codes for supercomputers by leveraging vector instructions, specifically focusing on the potential of ARM's upcoming SVE ISA to enhance parallelism.

## Contribution

It introduces the concept of SVE-enabling lattice QCD codes, highlighting the importance of vector instruction optimization for future ARM-based supercomputers.

## Key findings

- SVE offers significant parallelism potential for lattice QCD codes.
- Optimization strategies for vector instructions are crucial for high-performance computing.
- Future ARM processors are expected to improve supercomputing performance with SVE.

## Abstract

Optimization of applications for supercomputers of the highest performance class requires parallelization at multiple levels using different techniques. In this contribution we focus on parallelization of particle physics simulations through vector instructions. With the advent of the Scalable Vector Extension (SVE) ISA, future ARM-based processors are expected to provide a significant level of parallelism at this level.