Automatic Synthesis of Totally Self-Checking Circuits
Michael Garvie, Phil Husbands

TL;DR
This paper introduces an automatic method for synthesizing totally self-checking circuits from arbitrary logic, achieving lower overhead and guaranteeing self-testing, representing a significant breakthrough in concurrent error detection.
Contribution
It presents the first automatic synthesis method for TSC circuits from arbitrary logic, ensuring self-testing and reducing overhead compared to prior approaches.
Findings
Synthesized circuits have 23% overhead on average, significantly lower than previous methods.
Method guarantees TSC with respect to all gate input and output stuck-at faults.
Successfully applied to 11 benchmarks, demonstrating effectiveness and generality.
Abstract
Totally self-checking (TSC) circuits are synthesised with a grid of computers running a distributed population based stochastic optimisation algorithm. The presented method is the first to automatically synthesise TSC circuits from arbitrary logic as all previous methods fail to guarantee the checker is self-testing (ST) for circuits with limited output codespaces. The circuits synthesised by the presented method have significantly lower overhead than the previously reported best for every one of a set of 11 frequently used benchmarks. Average overhead across the entire set is 23% of duplication and comparison overhead, compared with an average of 69% for the previous best reported values across the set. The methodology presented represents a breakthrough in concurrent error detection (CED). The highly efficient, novel designs produced are tailored to each circuit's function, rather…
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Taxonomy
TopicsRadiation Effects in Electronics · Low-power high-performance VLSI design · Advanced Memory and Neural Computing
