Computational Assessment of Silicon Quantum Gate Based on Detuning Mechanism for Quantum Computing

TL;DR

This paper investigates the physics, variability, and scalability of silicon quantum gates based on detuning mechanisms, proposing methods to improve speed, fidelity, and reliability for quantum computing applications.

Contribution

It provides a detailed numerical analysis of silicon quantum gates, highlighting the importance of reducing variability and proposing control electronics to mitigate its effects.

Findings

High speed and fidelity achievable with low operation voltage.

Variability significantly impacts quantum gate performance.

Mitigation schemes are essential for scalable quantum computing.

Abstract

Silicon-based quantum computing has the potential advantages of low cost, high integration density, and compatibility with CMOS technologies. The detuning mechanism has been used to experimentally achieve silicon two-qubit quantum gates and programmable quantum processors. In this paper, the scaling behaviors and variability issues are explored by numerical device simulations of a model silicon quantum gate based on the detuning mechanism. The device physics of quantum gates modulation, tradeoff between device speed and quantum fidelity, and impact of variability on the implementation of a quantum algorithm are examined. The results indicate the attractive potential to achieve high speed and fidelity silicon quantum gates with a low operation voltage. To scale up, reducing the device variability and mitigating the variability effect are identified to be indispensable for reliable implementing a quantum computing algorithm with the silicon quantum gates based on the detuning mechanism. A scheme to use the control electronics for mitigating the variability of quantum gates is proposed.