Level-1 Track Finding with an all-FPGA system at CMS for the HL-LHC

TL;DR

This paper presents an all-FPGA hardware system developed for real-time Level-1 track finding at CMS during HL-LHC, addressing high data throughput and low latency requirements with innovative pattern recognition algorithms.

Contribution

It introduces a novel all-FPGA system with a time-multiplexed architecture for efficient track finding in high-rate collider environments, including algorithm design and hardware implementation details.

Findings

Successful implementation on customized FPGA electronics.

Achieved low-latency track reconstruction within 4 microseconds.

Demonstrated capability to handle 40 MHz collision data rate.

Abstract

With the High Luminosity LHC upgrades, incorporating tracking information into the CMS Level-1 trigger becomes necessary in order to maintain a manageable trigger rate and good trigger performance e.g. to retain thresholds for electroweak physics. The main challenges Level-1 track finding faces are the large data throughput from the detector at a collision rate of 40 MHz and a 4 microsecond latency budget to reconstruct charged particle tracks with sufficiently low transverse momentum to be used in the Level-1 trigger decision. Dedicated all-FPGA hardware systems with time-multiplexed architecture have been developed for track finding to address these challenges. The algorithm and performance of the pattern recognition and particle trajectory determination are discussed. The implementation on customized electronics with commercially available FPGAs is presented as well.