# DeCoILFNet: Depth Concatenation and Inter-Layer Fusion based ConvNet Accelerator

## TL;DR

This paper introduces DeCoILFNet, an FPGA-based CNN accelerator that enhances throughput and reduces memory access by exploiting intra-layer parallelism and inter-layer fusion, achieving significant speedups over existing solutions.

## Contribution

The paper presents a novel FPGA architecture, DeCoILFNet, combining depth concatenation and inter-layer fusion to improve CNN acceleration efficiency.

## Key findings

- 30X faster than a 3.5GHz Intel Xeon implementation
- Reduces external memory access by 11.5X
- Over 2X speedup compared to previous FPGA accelerators

## Abstract

Convolutional Neural Networks (CNNs) are rapidly gaining popularity in varied fields. Due to their increasingly deep and computationally heavy structures, it is difficult to deploy them on energy constrained mobile applications. Hardware accelerators such as FPGAs have come up as an attractive alternative. However, with the limited on-chip memory and computation resources of FPGA, meeting the high memory throughput requirement and exploiting the parallelism of CNNs is a major challenge. We propose a high-performance FPGA based architecture - Depth Concatenation and Inter-Layer Fusion based ConvNet Accelerator - DeCoILFNet which exploits the intra-layer parallelism of CNNs by flattening across depth and combines it with a highly pipelined data flow across the layers enabling inter-layer fusion. This architecture significantly reduces off-chip memory accesses and maximizes the throughput. Compared to a 3.5GHz hexa-core Intel Xeon E7 caffe-implementation, our 120MHz FPGA accelerator is 30X faster. In addition, our design reduces external memory access by 11.5X along with a speedup of more than 2X in the number of clock cycles compared to state-of-the-art FPGA accelerators.