# Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing

## TL;DR

This paper presents an improved implementation of BISMO, a bit-serial matrix multiplication overlay for FPGAs, achieving higher performance and better resource utilization for reconfigurable computing applications.

## Contribution

It introduces a scaled-up architecture for BISMO on Xilinx FPGAs that enhances performance and resource efficiency for variable-precision matrix multiplication.

## Key findings

- Achieved 15.4 binary TOPS peak performance on Ultra96 FPGA.
- Optimized utilization of 6-LUTs in the FPGA architecture.
- Demonstrated scalability of BISMO for reconfigurable computing.

## Abstract

Matrix-matrix multiplication is a key computational kernel for numerous applications in science and engineering, with ample parallelism and data locality that lends itself well to high-performance implementations. Many matrix multiplication-dependent applications can use reduced-precision integer or fixed-point representations to increase their performance and energy efficiency while still offering adequate quality of results. However, precision requirements may vary between different application phases or depend on input data, rendering constant-precision solutions ineffective. BISMO, a vectorized bit-serial matrix multiplication overlay for reconfigurable computing, previously utilized the excellent binary-operation performance of FPGAs to offer a matrix multiplication performance that scales with required precision and parallelism. We show how BISMO can be scaled up on Xilinx FPGAs using an arithmetic architecture that better utilizes 6-LUTs. The improved BISMO achieves a peak performance of 15.4 binary TOPS on the Ultra96 board with a Xilinx UltraScale+ MPSoC.