High Performance GNR Power Gating for Low-Voltage CMOS Circuits

TL;DR

This paper introduces a robust power gating design using Graphene Nano-Ribbon FETs (GNRFETs) for low-voltage CMOS circuits, aiming to improve delay and wake-up time issues in traditional designs.

Contribution

It proposes a novel GNRFET-based power gating structure that addresses delay and wake-up time drawbacks in low-voltage CMOS circuits, validated through 16nm technology benchmarks.

Findings

Reduced leakage power compared to traditional designs

Improved wake-up time and delay performance

Effective multi-mode power gating structures

Abstract

A robust power gating design using Graphene Nano-Ribbon Field Effect Transistors (GNRFET) is proposed using 16nm technology. The Power Gating (PG) structure is composed of GNRFET as a power switch and MOS power gated module. The proposed structure resolves the main drawbacks of the traditional PG design from the point of view increasing the propagation delay and wake-up time in low voltage regions. GNRFET/MOSFET Conjunction (GMC) is employed to build various structures of PG, GMCPG-SS and GMCPG-NS. In addition to exploiting it to build two multi-mode PG structures. Circuit analysis for CMOS power gated logic modules ISCAS85 benchmark of 16nm technology is used to evaluate the performance of the proposed GNR power switch is compared to the traditional MOS one. Leakage power, wake-up time and power delay product are used as performance circuit parameters for the evaluation.