A 256kb 9T Near-Threshold SRAM With 1k Cells per Bit-Line and Enhanced Write and Read Operations

TL;DR

This paper introduces a 9T SRAM cell with enhanced read stability and write-ability, enabling lower operating voltages and higher cell density, outperforming conventional 6T SRAM in power, stability, and area efficiency.

Contribution

A novel 9T SRAM cell design that significantly improves read stability and reduces minimum operating voltage, enabling higher density and lower power operation compared to traditional 6T SRAM.

Findings

Increases Read SNM by 219% at 300mV

Reduces VDDmin to 350mV from 725mV in conventional SRAM

Decreases write and read power by over 90% at minimum VDD

Abstract

In this paper, we present a new 9T SRAM cell that has good write-ability and improves read stability at the same time. Simulation results show that the proposed design increases Read SNM (RSNM) and Ion/Ioff of read path by 219% and 113%, respectively at supply voltage of 300mV over conventional 6T SRAM cell in a 90nm CMOS technology. Proposed design lets us to reduce minimum operating voltage of SRAM (VDDmin) to 350mV, whereas conventional 6T SRAM cannot operate successfully with acceptable failure rate at supply voltages bellow 725mV. We also compared our design with three other SRAM cells from recent literature. To verify the proposed design, a 256kb SRAM is designed using new 9T and conventional 6T SRAM cells. Operating at their minimum possible VDDs, the proposed design decreases write and read power per operation by 92%, and 93%, respectively over the conventional rival. Area of proposed SRAM cell is increased by 83% over conventional 6T one. However, due to large Ion/Ioff of read path for 9T cell, we are able to put 1k cells in each column of 256kb SRAM block, resulting in the possibility for sharing write and read circuitries of each column between more cells compared to conventional 6T. Thus, area overhead of 256kb SRAM based on new 9T cell is reduced to 37% compared to 6T SRAM.

Figures

Tables

Table 1. TABLE I : Minimum supply voltage for write, read, access, and data retention and V ​ D ​ D m ​ i ​ n 𝑉 𝐷 subscript 𝐷 𝑚 𝑖 𝑛 VDD_{min} (V).

Design	WRE9T	WRE8T	6T	ST-2	WEN	I.A.6T
Read	0.320	0.430	0.725	0.340	0.355	0.390
Access	0.310	0.405	0.555	1.20⋆	1.20⋆	0.375
Write	0.340	0.320	0.455	0.375	0.315	0.480
Retention	0.350	0.350	0.350	0.375	0.350	0.275
$VD{D}_{min}$	0.350	0.430	0.725	1.20	1.20	0.480

Table 2. TABLE II : Single cell area comparison for different SRAM cells in 90nm CMOS technology.

Design	WRE9T	WRE8T	6T	ST-2	WEN	I.A.6T
Area($\mu$m2)	3.72	2.89	2.03	3.99	3.45	3.72

Table 3. TABLE III : Operating Parameters Comparison for 256kb SRAM Using WRE9T and Conv. 6T Cells.

Design	WRE9T@350mV	6T@725mV
Read Power ($\mu$W)	25.68	376.5
Write Power ($\mu$W)	32.75	456.12
Read Delay (ns)	13.205	1.29
Write Delay (ns)	12.88	1.76
Area (mm2)	1.18	0.86

Table 4. TABLE IV : Overall design metric comparison.

Design metrics	The best
$I_{on}/I_{off}$	WRE9T
RSNM	WRE9T
HSNM	ST-2
WNM	WRE9T
$VD{D}_{min}$	WRE9T
Leakage Power @$VD{D}_{min}$	WRE8T
Cell Area	6T

Equations

$$I_{Dsub}=I_{s}10^{\frac{V_{GS}-V_T+\lambda V_{DS}}{S}}(1-10^{-\frac{\eta V_{DS}}{S}})$$

$$I_{Dsub}=I_{s}10^{\frac{V_{GS}-V_T+\lambda V_{DS}}{S}}$$

$$I_{22}=I_{s}10^{\frac{-V_T+\frac{{\lambda }^2+\lambda +1}{2\lambda +1}{V}_{DD}}{S}}$$

$$I_{31}=I_{s}10^{\frac{-V_T+\frac{{\lambda }^3+{\lambda }^2+2\lambda +1}{3{\lambda }^2+3\lambda +1}{V}_{DD}}{S}}$$

$$I_{32}=I_{s}10^{\frac{-V_T+\frac{{\lambda }^3+2{\lambda }^2+\lambda }{3{\lambda }^2+3\lambda +1}{V}_{DD}}{S}}$$

$$V_T=V_{T0}+\gamma (\sqrt{|-2{\varphi }_F+V_{SB}|}-\sqrt{|-2{\varphi }_F|})$$

Full text

I Introduction

for MANY years, there was little interest in low power design and design trend was towards increasing the speed and working frequency of digital systems [1]. Recently some applications such as implantable devices in man’s body, portable applications and WSNs that need low-power circuits, increase the importance of low-power and ultra-low-power design [2].

SRAMs are an important part of most of the digital chips and consume a large percent of area and power of each chip [3], so decreasing the power and area of SRAMs can lead to decreasing the overall power and area of chips. Due to quadratic relation between power and supply voltage of transistors [4], one effective and common method to reduce the power consumption is to decrease the supply voltage. By further decreasing the supply voltage, it will be lower than threshold voltage of transistors, so the circuit will operate in sub-threshold region. Unfortunately conventional designs cannot work properly in sub-threshold region, so new configurations are needed to let the digital systems work successfully in this region. In this paper, we present a new 9T SRAM cell that solves the problems of write and read operations at low supply voltages, thus let the SRAM to operate at smaller supply voltages.

The rest of this paper is organized as follows: In Section II write and read operations problems of conventional 6T SRAM cell is mentioned and some recently published SRAM cells for resolving this problems are discussed. Section III presents our new design for SRAM cell. In Section IV, simulation results for our design and also other SRAM cells are compared. Finally, Section V concludes the manuscript.

II Problem statement and previously write and read enhanced SRAM cells

Conventional 6T SRAM cell faces problems of write failures at low supply voltages [5]. Actually, at low supply voltages weak write-access transistors in this cell cannot overcome to the strong feedback of inverters of the cell. So, in duration of write operation, access transistors cannot enforce the input to the desired cell.

Also at low supply voltages, conventional 6T SRAM cell faces read failures during read operation, and content of the selected cell is subject to change with large likelihood. However, it is possible to increase the read stability of conventional 6T cell by using minimum size access transistors, but this will degrade write-ability of this cell. Moreover, problem of small Read Static Noise Margin (RSNM) is left un-resolved. Another challenge of conventional 6T SRAM cell is small ${I_{on}}/{I_{off}}$ of read-access transistors that doesn’t let integrate large number of cells in each column of SRAM array. At supply voltage of 200mV in a 0.13$\mu$m technology, this ratio decreases to 240 at the worst case pattern for data of cells in the same bit-line [6]. It means that at this supply voltage, number of cells sharing same bit-line must be enough smaller than 240 that the difference between ON current of selected cell and accumulated OFF currents of other cells can be distinguished by available sense amplifiers. It is desired to increase ${I_{on}}/{I_{off}}$ for read-access path to integrate more cells in the same bit-line. Integration of more SRAM cells in the same bit-line makes it possible to share write and read circuitries of each column between more cells, translating to saving area and power of these circuitries and hence total area and power of SRAM block.

To benefit from power lowering with supply voltage scaling, several designs were proposed in recently published papers. Some of them tried to resolve challenges related to write operation to improve the write-ability at small supply voltages. In general, there are two possible solutions to improve write-ability; the first one is to make write-access transistors stronger during write operation. Authors in [7] used boosted (larger) voltage to control the write-access transistors during write operation, and authors in [8] make access transistors stronger by employing reverse short channel effect (RSCE) (using access transistors with larger (3X) channel length). The second solution to improve write-ability of conventional SRAM cell is to make the feedback loops between inverters of the cell weaker or to brake this feedback loop during write operation [9, 10, 6, 11, 12].

Some other designs tried to resolve problems related to read operation. To decrease the read failure probability, a 7T [13] and two 8T SRAM cells were proposed [14, 15]. To increase Read SNM (RSNM), several forms of buffering read (sensing voltage of internal node by gate of a transistor) were proposed [16, 17, 18, 13]. In these cells due to buffering read operation, RSNM is increased to the level of Hold SNM (HSNM), but in all of these designs, problem of small ${I_{on}}/{I_{off}}$ for read-access path is still remained un-resolved.

Authors in [19, 20, 21] used a modified version of buffering read that improves ${I_{on}}/{I_{off}}$ of read access path and RSNM at the same time.

III Our Proposed Design

In previous section, some techniques used in several SRAM cells were introduced. Each of these cells can improve write or read operations at lower supply voltages. There are some SRAM cells proposed in recently published papers that can improve write and read operations at the same time. Kulkarni and Roy changed the design in [22], and proposed a modified version of schmitt-trigger based SRAM cell (ST-2 hear after)[23]. This SRAM cell increases write-ability due to stacked transistors in the inverters of the cell and improves read operation by using individual added access transistors. Wen et al. [24] introduced single-ended 8T SRAM cell (WEN cell hear after) that can improve write and read operations at the same time. We proposed an 8T SRAM cell in our previous work [25] that improves write-ability due to ability of the cell to make one of the inverters of the cell weaker during write operation (WRE8T hear after). This cell also improves read operation due to single ended write and read operations that let to avoid access transistors sizing conflict. Fig. 1 shows different designs for SRAM cell based on the improvements that they suggest. Fig. 2 shows the circuit diagram of previously write and read enhanced SRAM cells.

In this paper, we present a new 9T SRAM cell that improves write and read operations at the same time. In the next sub-sections we will explain the write and read enhanced techniques used in our proposed Write and Read Enhanced 9T SRAM cell (called WRE9T).

III-A Write Enhancement Techniques in Proposed SRAM Cell

In the SRAM cell used in [25], one NMOS and one PMOS transistor were added to each cell of SRAM that become OFF during write operation and provide floating power and ground rails. In this cell, to control the gate of added NMOS transistor, a separate word-line is needed. These added transistors and word-line impose area overheads. The point is that, it is not necessary to add these two transistors to each cell to have floating power and ground rails. We can use one NMOS and one PMOS transistor that provide these floating rails and distribute these rails among the sharing cells. There are some possible strategies for sharing the floating rails. Fig. 3 shows three architectures. In parts (a) and (b), there are cells that are not selected but become weaker during write operation. The less stable cells are shown with light color in this figure and are called half selected cells (their WL are 0 but power rail of them are floated). Simulations at supply voltage of 500mV show that mean of SNM of half selected cells in 1000 runs of Monte Carlo simulations is 0.33mV while it is 167.4mV for not-selected cells. This margin is very small and even at room temperature, thermal noise can flip the content of the cell.

Authors in [12] used architecture of Fig. 3 Part(b) for designing the SRAM and shared power line of all cells in the same column. In this design there is a possible state for content of the cells in the same column, that will lead to increased write power due to existence of sneaky current. This strategy and sneaky current are shown in Fig. 4. In this figure, only the left inverter of the SRAM cells are shown. As seen, to write ’0’ to the selected cell, if voltage of right internal nodes in the other cells sharing the column are set to ’0’, the PMOS transistors in these cells will be ON and let the sneaky current to pass through shared floating line and discharge the voltage of internal nodes in not-selected cells. Thus, activity of nodes and hence, write power will increase. To test the effect of this sneaky current on power consumption, a column of SRAM cells with one selected and 64 other non-selected cells were designed using this architecture and write power for writing ’0’ was extracted. Two strategies were considered. Case 1: voltage of right internal nodes in non-selected cells are ’0’ so sneaky current will exist, and case 2: voltage of right internal nodes in non-selected cells are ’Vdd’ so, path for sneaky current will not exist. Extracted power for case 1 is $1.18\mu$W and for case 2 is 0.1$\mu$W.

Due to discussed problems for architectures of Fig. 3 Parts (a) and (b), we choose third architecture (Fig. 3 part (c))for implementing our SRAM. Even in this architecture, state of half selection will exist if we decide to select each bit individually. To solve the disturbance in this state, we apply our half selection disturb-free scheme introduced in [25]. In this scheme, before first write operation in consecutive writes, the content of each cell in the selected row are read and then, using embedded inverters in each column, they are written back on the corresponding write bit-lines.

III-B Read Enhancement Techniques in Proposed SRAM Cell

One method to increase RSNM is sensing voltage of internal nodes of SRAM cell through gate of a transistor in read operation. The simplest way of buffering is using two transistors that one of them (buffer transistor) senses internal voltage of SRAM cell, and the other one is controlled by RWL signal [17]. In the case that buffer transistor is ON, for un-selected cell, leakage current is large. In [26, 27] three transistors are used in read path. Depending on the internal voltage of SRAM cell, there are two or three OFF transistors in read path for un-selected SRAM cells. Equation (1) shows the dominating part of leakage current, that is subtreshold current [28]. For $V_{DS}$ larger than 50mV, we can ignore the second term to reach to Equation (2) [28].

[TABLE]

[TABLE]

Now, the worst case leakage current for two and three stacked transistors (one of stacked transistors is ON) can be expressed by Equations (3), and (4), respectively. Assuming that $V_{T}=300mV$, $\lambda=1.5$, and $S=80mV$ (typical values [28]), for VDD=1.0V, ratio of the worst case leakage current for three stacked transistors ($I_{31}$), to the worst case of two stacked transistors ($I_{22}$) can be expressed by $I_{31}/I_{22}=10^{\frac{-\lambda^{4}-3\lambda^{3}-2\lambda^{2}}{6\lambda^{3}+9\lambda^{2}+5\lambda+1}VDD/S}=10^{-5}$. As seen, leakage current is decreased by exponential order if one stacked transistor is added to read path.

In [26], one of three stacked transistors in the read path is shared among all cells in the array, so it is OFF only in idle modes, so, the worst case for leakage current flowing through read path is that two of stacked transistors are ON and one of them is OFF. Leakage current for this case can be expressed by Equation (5), that shows 80% increasing compared with Equation (4).

[TABLE]

[TABLE]

[TABLE]

In addition to this increment of leakage current in SRAM cell of [26], there is a possible state that read bit-line will be discharged falsely. Fig. 5 shows SRAM cells used in [26]. In Fig. 6, a possible state is illustrated that can lead to falsely discharging the bit-lines and cause read fault. In this figure, RBL_1 bit-line must not be discharged because stored voltage in the second cell in the first row is 0; but the shown sneaky current can discharge this bit-line and leads to read fault.

In SRAM cell of [27], the above sneaky current does not exist, and for not selected cells, there are two or three OFF transistors in the read path, so leakage current for not selected cells is small. However, leakage current for a selected SRAM cell that are storing a ’0’ on the right internal node is similar to the case that was expressed by Equation (5); because in this case, there are two ON and one OFF transistors in the read path. So, in this case large leakage current can falsely discharge the read bit-line.

To solve the challenges of SRAM cells used in [26] and [27], we are proposing a new design for SRAM cell. Fig. 7 shows circuit diagram of our 9T SRAM cell. Fig. 8(a) shows the read path of our design. In this design, added PMOS transistor M9 is ON for not selected cells so the voltage of node Qc will rise to reach VDD for these cells. This will reduce the leakage current passing through M6 for two reasons. The first reason is that by increasing the voltage of source of M6, its threshold voltage will increase according to Equation (6) [4]. Increasing $V_{th}$ will decrease the sub-threshold leakage current $I_{sub}$ (that is the main component of leakage current) due to Equation (1). The second reason behind decreasing leakage current is that by increasing voltage of source of M6, $V_{GS}$ of this transistor will decrease and due to Equation (1) this will reduce sub-threshold current $I_{sub}$ exponentially.

As mentioned earlier, challenge of design used in [27] is that large leakage current flows through read access path for an specific data pattern in selected cells. In this case, despite the stored data in the selected cell, leakage current can discharge the read-bit-line capacitance falsely. In our design, for selected cells, added PMOS transistor M9 is OFF but still passes some leakage current to node Qc. This will increase voltage of node Qc a little, and due to Equations (1) and (6), reduce leakage current flowing through M6.

[TABLE]

Fig. 8(d) shows ON to OFF current ratios for read buffered transistors in read path for the three designs (Typical Corner, and T=27 ∘C). In this figure, voltage of internal node is assumed to be VDD. As seen, ${I_{on}}/{I_{off}}$ of read path for our proposed design is considerably larger than the two others. For example, at VDD=0.8V, ${I_{on}}/{I_{off}}$ of WRE9T design is 8.66 times larger than 9T cell in [27]. Thus, it is possible to integrate larger number of cells sharing same bit-line in our design compared to two others, resulting in saving the area and power of peripheral circuits used for each column in SRAM array.

IV Simulation Results and Discussion

Since our proposed SRAM cell in this paper is write and read enhanced, thus in this part we extract and compare different working parameters of this cell with other write and read enhanced SRAM cells and also conventional 6T SRAM cell. HSPICE 2011 was used for simulations and circuits were designed in a 90nm industrial CMOS technology.

To make the comparison of conventional 6T SRAM cell with our proposed SRAM cells more fair, we also consider Iso-Area 6T (I.A.6T) SRAM cell [23]. In I.A.6T SRAM cell, transistors were up-sized so that the area of this cell becomes equal to WRE9T SRAM cell.

IV-A ${I_{on}}/{I_{off}}$* of read path*

Fig. 9 shows distribution of ${I_{on}}/{I_{off}}$ for proposed SRAM cell and conventional one in presence of process variation at supply voltage of 300mV. As seen, mean of ${I_{on}}/{I_{off}}$ for proposed cell is larger than conv. 6T. Worst case ratio for proposed design is 1080 and is 78 for 6T.

For the case that voltage of storage node is such that the related bit-line should not be discharged, leakage current of selected and not selected cells become very important. As the leakage of read path become larger, voltage of read bit-line decreases much faster and this will lead to read the stored data falsely. Fig. 10 shows voltage of read bit-line (for differential cells, voltage of the bit-line that should not be discharged) when it should not be discharged at supply voltage of 500mV. As seen, voltage drop for WRE9T cell since read word-line asserted ($@$ 980 ns) until 120 ns later, is almost 7mV, whereas for the best of others (conventional 6T), this voltage drop is almost 250mV. Voltage of read bit-line for ST-2 and WRE8T reach to VDD/2 after 30ns. Thus, if voltage of this bit-lines are read after this time, read error will occur. In our design, by using stacking effect and also by adding the PMOS transistor M9, leakage current through read path is very small. In the read path of SRAM cells used in [19] and [20] also the path between read bit-line and ground is broken, so it is expected that voltage drop of read bit-line for these cells becomes small similar to our design. Fig. 11 shows the voltage of read bit-line for WRE9T cell and those of [19] and [20]. Voltage drop for Calhoun et al. cell [19] after 120ns is almost 127mV and remains above VDD/2. Voltage drop of Kim et al. cell [20] is almost equal to WRE9T cell and is acceptable.

IV-B Read, Write, and Hold SNMs

One of the most important drawbacks of conventional 6T SRAM cell is small read SNM (RSNM) at low supply voltages. This does not let scaling of supply voltage and going to sub-threshold region to benefit from power saving of it [29]. Fig. 12 shows distribution of RSNM for WRE9T and 4 other SRAM cells at supply voltage of 500mV. Mean of RSNM for our design is better than conventional and ST-2 by 2.53X and 1.23X, respectively. In WEN SRAM cell [24], voltage of left node in the cell is kept floating during read operation. At typical corner and room temperature, leakage of PMOS pull up transistors in this cell is considerable that leads to destroying the dynamic voltage of left storage node. Thus, RSNM for this cell is very small at these conditions (Mean is 0.3mV and sigma is 1.8mV).

Fig. 14 shows write noise margin (WNM) of compared cells at three different supply voltages. WNM is a metric to measure the write-ability of SRAM cells. Having larger WNM for a cell means that write-ability is larger for the cell. In WRE9T, WRE8T and WEN SRAM cells, feedback loops in the cells are interrupted during write operation that results in more successful write operations for these cells. This is the reason of larger WNM for these three SRAM cells in Fig. 14.

Hold SNM (HSNM) is not such challenging and is normally large enough at low supply voltages. Fig. 13 shows mean and sigma HSNM for different SRAM cells at supply voltage of 500mV. Except ST-2 cell that have better HSNM compared to others, HSNMs of others are not far from each other, and the difference between mean of the best design and the worst one is about 7mV.

IV-C Minimum Operating Voltage; $VDD_{min}$

To benefit from power saving of voltage scaling, it is desired to design SRAMs that can operate successfully at lower supply voltages. There are two different methods to determine minimum supply voltage for SRAMs. The first one is based on SNM [23] that does not capture the transient behaviour of the cell. The second one considers the transient behaviour of the cell but uses some approximations that lead to large errors at the tail of the distribution where the sensitive failure probabilities exist [30]. In this paper, minimum operating voltage is extracted while the circuits operate at their real operating modes so that transient behaviour is captured. Assuming not having error correcting code (ECC) in data, and considering the size of SRAM to be 1Mb, the failure probability is considered $10^{-6}$ [30].

To have accurate results and to model the process variation effect, Monte Carlo (MC) simulations were used. In this simulations different parameters such as threshold voltage, channel length, gate oxide thickness, carrier mobility, and channel doping concentration were varied with Gaussian distributions.

To extract the failure probability in above simulations, dynamic criteria proposed in [31] was used and the outputs were measured at the end of the operation cycle. Table I shows minimum operating voltages for different modes of operation. $VDD_{min}$ for each design is the maximum of these minimum voltages. As seen, $VDD_{min}$ for our proposed design, WRE9T is lower than others.

IV-D Power Consumption

IV-D1 Leakage Power

In Section IV-C, minimum operating voltage of different SRAM cells were extracted. Assuming that the mentioned SRAMs are used in low-power circuits, they are expected to operate at their $VDD_{min}$; thus, we extracted leakage power of each cell at its $VDD_{min}$. Fig. 15 shows the leakage power of different cells. These results were extracted in typical corner and at temperature of 110∘C.

IV-D2 Total Power Consumption for Single Write Operation

Fig. 16 shows power consumption for single write operation for different SRAM cells. This power consumption is average of power consumption for writing one ’0’ and one ’1’ to the desired SRAM cell. As seen, power consumption for WRE8T, WRE9T, and WEN SRAM cells are smaller than three others. This is mainly due to single ended write operation in these SRAM cells, that leads to have smaller charging-discharging on write-bit-lines (for single ended cells there is one write-bit-line compared with differential ones that there are two write-bit-lines).

IV-E Layout Area

Fig. 17(a) shows the layout of the proposed cell and Fig. 17(b) shows the layout of conventional 6T SRAM cell in a 90nm industrial CMOS technology. Table II shows area of compared SRAM cells in this technology. As seen, conventional design has the minimum area, whereas ST-2 cell occupies larger area in the silicon.

Area of proposed WRE9T cell is larger than 6T by 83%. However, simulation results for I.A.6T shows that, in the same consumption of silicon area for WRE9T and I.A.6T, $VDD_{min}$, read SNM, $I_{on}/I_{off}$ for read access path, are better for proposed design. Only hold SNM of I.A.6T is better than WRE9T cell. Therefore, conventional 6T SRAM cell with the same area cannot have capabilities similar to WRE9T. However, there is a drawback for WRE9T in physical implementation compared with conventional 6T SRAM cell; layout of WRE9T cell is not fully symmetric, and will be subject to systematic differences in processing variation.

IV-F A 256kb SRAM

We designed a 256kb SRAM using proposed WRE9T, and conventional 6T SRAM cells. As mentioned in Section IV-A, worst case value of ${I_{on}}/{I_{off}}$ for WRE9T and 6T cells are 1080, and 78, respectively. Thus, we put 1k cells in each column of the proposed SRAM block and 64 cells in each column of SRAM block using 6T cells. Table III lists write and read power and delays for both of these SRAMs. We have mentioned the results assuming that each SRAM is operating at its minimum possible supply voltage. In this table, write delay is the time between activation of decoder until voltages of internal nodes of selected cell become equal. Read delay is the time between activation of decoder until 50mV voltage difference between two bit-lines occurs [18] (for WRE9T that there is one bit-line for read operation, this difference is between voltage of read bit-line and Vdd). Write power and write delay reported here are average of writing 1 and 0, and read power is average of reading 1 and 0. However, since we assume that bit-line is pre-charged to Vdd, read delay is the delay for reading 0.

There are several papers such as [32, 33, 6] that discussed about single ended and differential read operations in SRAM cells, and their differences in different characteristics especially read delay. These comparisons and statements can be applied for all single ended and differential SRAM cells, and also to our single ended and conventional differential SRAM cells. However in this paper, we mostly focus on characterizing and comparing single SRAM cells. Thus, in the measurements of read delay, we did not consider the effect of sense amplifiers.

As seen, proposed design consumes lower power consumption for both read and write operations. Write and read circuitries of each column of SRAM block are shared among more cells when using new 9T cells compared to conventional 6T cells. This results in reducing area overhead of 256kb SRAM based on new 9T SRAM cells from 83% (for comparing single SRAM cells) to 37% compared to block design with conventional 6T.

In this section, several electrical design metrics were considered and the SRAM cells were compared and the best designs for each criterion were determined as listed in Table IV. Our proposed design WRE9T is the best in four metrics. Thus, we conclude this design can be the best choice to operate at low voltages.

V Conclusion

In this paper a new 9T SRAM cell was presented. This SRAM cell improves write-ability and read stability at the same time. In this SRAM cell, $I_{on}/I_{off}$ of read access path is increased considerably that lets to integrate more cells in the same column of SRAM array. This property allows to share write and read peripheries that can directly translate to saving area and power. Proposed design decreases minimum possible operating voltage of SRAM by 375mV over conventional 6T and by 130mV over Iso Area 6T (I.A.6T) SRAM cell. Area of the proposed cell is larger than 6T cell by 83%. This overhead is reduced to only 37% by the potential of sharing write and read circuitry of each column in a 256kb SRAM.