# PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits

## TL;DR

This paper introduces PBMap, a dynamic programming algorithm for path balancing technology mapping in SFQ and CMOS circuits, significantly reducing balancing overhead and improving circuit reliability.

## Contribution

It presents a novel dynamic programming algorithm for optimal path balancing in SFQ circuits, outperforming existing mappers in efficiency and effectiveness.

## Key findings

- Reduces balancing overhead by up to 2.7 times.
- Achieves an average of 21% improvement over state-of-the-art methods.
- Effective for both SFQ and CMOS circuits.

## Abstract

This paper presents a path balancing technology mapping algorithm, which is a new algorithm for generating a mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing technology mapping is required in dc-biased Single Flux Quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing technology mapping which generates optimal solutions for dc-biased SFQ (e.g. Rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general Directed Acyclic Graph (DAG) structure. Experimental results show that our path balancing technology mapper reduces the balancing overhead by up to 2.7 times and with an average of 21% compared to the state-of-the-art academic technology mappers.