# A Complexity Reduction Method for Successive Cancellation List Decoding

## TL;DR

This paper presents a hardware-efficient method for SCL decoding that reduces complexity by using a specialized sorting scheme, leading to significant hardware savings without increasing decoding latency.

## Contribution

The paper introduces a novel sorting scheme for SCL decoders that halves the number of multiplexers needed, with FPGA implementations demonstrating substantial hardware efficiency improvements.

## Key findings

- Reduces multiplexers from L to (L/2+1) in hardware implementations.
- Achieves significant hardware savings, especially for large list sizes.
- Maintains decoding latency despite complexity reduction.

## Abstract

This brief introduces a hardware complexity reduction method for successive cancellation list (SCL) decoders. Specifically, we propose to use a sorting scheme so that L paths with smallest path metrics are also sorted according to their path indexes for path pruning. We prove that such sorting scheme reduces the input number of multiplexers in any hardware implementation of SCL decoding from L to (L/2+1) without any changes in the decoding latency. We also propose sorter architectures for the proposed sorting method. Field programmable gate array (FPGA) implementations show that the proposed method achieves significant gain in hardware consumptions of SCL decoder implementations, especially for large list sizes and block lengths.