Modeling Processor Idle Times in MPSoC Platforms to Enable Integrated DPM, DVFS, and Task Scheduling Subject to a Hard Deadline

TL;DR

This paper introduces a new modeling approach for idle times in MPSoC platforms, enabling integrated DPM, DVFS, and task scheduling to optimize energy efficiency while meeting hard deadlines.

Contribution

It presents a novel MILP formulation for modeling idle intervals in MPSoCs, integrating DPM, DVFS, and task scheduling, along with a heuristic solution method.

Findings

The MILP model effectively captures idle intervals for energy optimization.

The heuristic provides near-optimal solutions with reduced computation time.

Experimental results demonstrate improved energy efficiency under real-time constraints.

Abstract

Energy efficiency is one of the most critical design criteria for modern embedded systems such as multiprocessor system-on-chips (MPSoCs). Dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM) are two major techniques for reducing energy consumption in such embedded systems. Furthermore, MPSoCs are becoming more popular for many real-time applications. One of the challenges of integrating DPM with DVFS and task scheduling of real-time applications on MPSoCs is the modeling of idle intervals on these platforms. In this paper, we present a novel approach for modeling idle intervals in MPSoC platforms which leads to a mixed integer linear programming (MILP) formulation integrating DPM, DVFS, and task scheduling of periodic task graphs subject to a hard deadline. We also present a heuristic approach for solving the MILP and compare its results with those obtained from solving the MILP.

Figures

Tables

Table 1. Table 1. Task Graphs Characteristics and Corresponding Energy Consumption Values Obtained from iSCT versus iSC+T

Task	No. of	Total Workload of	Td	Total Energy		iSCT versus iSC+T
Graph	Tasks	Tasks in Processor	(ms)	Consumption (mJ)		Energy Saving
		Cycles ($\times {10}^6$)		iSC+T	iSCT	(%)
TGFF1	7	15.89	8	12.67	10.45	17.52
TGFF2	11	18.69	12	13.60	12.06	11.32
TGFF3	14	34.39	10	25.99	22.70	12.66
TGFF4	15	31.89	12	28.08	21.00	25.21
TGFF5	16	34.88	12	27.35	23.02	15.83
TGFF6	18	33.46	14	25.38	21.98	13.40
TGFF7	22	44.94	22	33.74	29.39	12.89
TGFF8	28	56.81	18	42.95	37.00	13.85

Table 2. Table 2. Idle Intervals Characteristics and No. of Used Processors for iSCT versus iSC+T

Task	No. of Idle Intervals		Total Idle time (ms)		No. of Used Processors
Graph	iSC+T	iSCT	iSC+T	iSCT	iSC+T	iSCT
TGFF1	5	3	21.62	24.00	3	1
TGFF2	4	3	35.79	36.00	4	1
TGFF3	6	3	17.53	21.22	4	2
TGFF4	10	3	27.16	29.00	4	2
TGFF5	7	3	25.21	29.00	4	2
TGFF6	8	3	34.13	34.13	4	2
TGFF7	10	3	58.63	58.64	4	2
TGFF8	10	3	34.87	36.96	4	2

Equations

$$P=a{f}^{\alpha }+bf+c,$$

$$E_{cycle}=a{f}^{\alpha -1}+b+\frac{c}{f}.$$

$$E_{idle}(I)=\left\{\begin{array}[]{cc}c\times I&\hskip 14.22636pt0\leq I<T_{be}\\ E_{sw}&\hskip 14.22636ptT_{be}\leq I<T_{d}\quad,\\ 0&\hskip 14.22636ptI=T_{d}\\ \end{array}\right.$$

$$T_{be}=\max (T_{sw},\frac{E_{sw}}{c}),$$

$$Du{r}_u=\sum _{i=1}^m\frac{N_{u,i}}{f_i},$$

$$\sum _{i=1}^m{N}_{u,i}=W_u,N_{u,i}\ge 0.$$

$$E_{task}(u)=\sum _{i=1}^m(N_{u,i}.(a{f}_i^{\alpha -1}+b+\frac{c}{f_i})).$$

$$S_u+Du{r}_u\le T_d,S_u\ge 0,$$

$$S_u+Du{r}_u\le S_v,\forall e(u,v)\in E.$$

$$P_{k,u}=\left\{\begin{array}[]{cc}1&\hskip 14.22636pt\textrm{if task u is assigned to processor k}\\ 0&\hskip 14.22636pt\textrm{otherwise}\\ \end{array}\right..$$

$$\sum _{k=1}^K{P}_{k,u}=1,\text{for }u=1,2,...,n.$$

$$O_{k,u,v}=\left\{\begin{array}[]{ll}1&\hskip 2.84526pt\textrm{if task u is scheduled immediately}\\ &\hskip 2.84526pt\textrm{ before task v on processor k}\\ &\\ 0&\hskip 2.84526pt\textrm{otherwise}\\ \end{array}\right..$$

$$\sum _{\begin{array}{c}v=1\\ v\ne u\end{array}}^{n+1}{O}_{k,u,v}=P_{k,u},\text{for }u=0,1,...,n$$

$$\sum _{\begin{array}{c}u=0\\ u\ne v\end{array}}^n{O}_{k,u,v}=P_{k,v},\text{for }v=1,2,...,n+1.$$

$$\begin{array}{r}\sum _{k=1}^K\sum _{u=1}^n\left(\left(S_u+Du{r}_u\right).O_{k,u,v}\right)\le S_v,\\ \text{for }v=1,2,...,n,v\ne u,\end{array}$$

$$\begin{array}{r}{S}_u+Du{r}_u-(1-O_{k,u,v})\times T_d\le S_v,\\ \text{for }u=1,2,...,n,\\ \text{for }v=1,2,...,n,v\ne u,\\ \text{for }k=1,2,...,K.\end{array}$$

$$I_v$$

$$\times (S_v-\sum _{k=1}^K\sum _{\begin{array}{c}u=1\\ u\ne v\end{array}}^n((S_u+Du{r}_u).O_{k,u,v})).$$

$$I_k^{\prime }$$

$$+\sum _{v=1}^n(O_{k,0,v}\times S_v).$$

$$\sum _{u=1}^n{E}_{task}(u)+\sum _{v=1}^n{E}_{idle}(I_v)+\sum _{k=1}^K{E}_{idle}(I_k^{\prime }).$$

$$E_{idle}(I_v)=S_v.(E_{sw})+(1-S_v).(c\times I_v),$$

$$\frac{I_v-T_{be}}{T_d}\le S_v\le \frac{I_v}{T_{be}},S_v\in \{0,1\}.$$

$$E_{idle}(I_k^{\prime })=U_k.[S_k^{\prime }.(E_{sw})+(1-S_k^{\prime }).(c\times I_k^{\prime })],$$

$$\frac{I_k^{\prime }-T_{be}}{T_d}\le S_k^{\prime }\le \frac{I_k^{\prime }}{T_{be}},S_k^{\prime }\in \{0,1\},$$

$$\frac{I_k^{\prime }-T_d}{Td}\le U_k\le \frac{I_k^{\prime }}{T_d},U_k\in \{0,1\}.$$

$$ran{k}_{up}(u)=Du{r}_u^{\ast }+\underset{v\in succ(u)}{\max }(ran{k}_{up}(v)),$$

Full text

Task Scheduling, Energy Optimization, DVFS, DPM, Real-time MPSoCs

††copyright: none††journalyear: 2019††copyright: acmlicensed††conference: 24th Asia and South Pacific Design Automation Conference; January 21–24, 2019; Tokyo, Japan††booktitle: 24th Asia and South Pacific Design Automation Conference (ASPDAC ’19), January 21–24, 2019, Tokyo, Japan††price: 15.00††doi: 10.1145/3287624.3287630††isbn: 978-1-4503-6007-4/19/01††ccs: Computer systems organization Embedded and cyber-physical systems††ccs: Computer systems organization Real-time systems††ccs: Theory of computation Scheduling algorithms††ccs: Theory of computation Integer programming††ccs: General and reference Design††ccs: General and reference Performance

1. Introduction

Energy consumption is one of the most important design criteria of computing devices, ranging from portable embedded systems to servers in data centers. Furthermore, with growing demand for high performance in embedded systems, architectures such as multiprocessor system-on-chip (MPSoC) are becoming more popular for many real-time applications. In order to reduce energy consumption in such embedded systems, two main techniques are used, namely, dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM). In DVFS, operating voltage and clock frequency of processors are adjusted based on workload characteristics. With DPM, processors are switched to a low power state (sleep mode) when they are not used for execution of any tasks (idle time/interval). This leads to the reduction of static power consumption. However, switching to a sleep mode has non-negligible time and energy overhead, and it only causes energy savings when the idle time of a processor is longer than a threshold called break-even time (gerards2013optimal, ).

There have been many research studies regarding reducing the energy consumption using DVFS and/or DPM. A major portion of these studies only considers DVFS for the energy optimization on single and multiprocessor platforms (aydin2001determining, ; huang2009energy, ; gerards2015interplay, ). Ref (nakada2017energy, ) has focused on DPM and has proposed an energy-efficient scheduling relying on minimizing the number of processor switching and maximizing the usage of energy-efficient cores in heterogeneous platforms. Some other papers have integrated scheduling of tasks with DVFS and then, at the final phase, have applied DPM wherever it was possible (srinivasan2007integer, ). However, with the increase in static power portion of the total power consumption of systems (huang2011applying, ), both DPM and DVFS should be integrated with scheduling of tasks for the sake of energy optimization. Reference (rong2006power, ) has combined DPM and DVFS for minimizing energy consumption of a uniprocessor platform performing periodic hard real-time tasks with precedence constraints. A major challenge of integrating DPM with the scheduling of tasks in a multiprocessor platform is formulating idle intervals and their associated energy consumption in the total energy consumption of the these platforms. The authors in (chen2014energy, ) have developed an energy-minimization formulation for a multiprocessor system considering both DVFS and DPM and solves it via mixed integer linear programming (MILP). However, one major assumption in their formulation is that the processor assignment for the tasks to be scheduled is known in advance. Furthermore, they only consider inter-task DVFS, i.e., the frequency of the processor stays constant for the entire duration of the execution of a task. However, when there is a set of discrete frequencies available for task execution (as that is the case in (chen2014energy, ) and also our work as we will see in Section 2.4), allowing intra-task DVFS and the usage of a combination of discrete frequencies for execution of tasks can result in more energy savings (gerards2013optimal, ).

In this paper, by proposing a method for modeling idle intervals in a multiprocessor system, we present an energy optimization MILP formulation integrating both DVFS and DPM with scheduling of real-time tasks with precedence and time constraints. By solving the MILP, for each task, we obtain the optimum processor assignment, execution start time, and the distribution of its workload among available frequencies of the processor. To the best of our knowledge, this is the first work that integrates both DVFS and DPM with scheduling of real-time periodic dependent tasks in a formulation that provides optimum values for all the aforementioned results simultaneously in a multiprocessor platform. We also present a heuristic approach for solving the model and compare its results with those obtained from solving the MILP. The rest of the paper is organized as follows: Section 2 explains the models used for the problem formulation and presents the formal problem statement. Section 3 presents the proposed method and MILP formulation. Section 4 provides the results. Finally, Section 5 concludes the paper and discusses future work.

2. Models and Problem Definition

2.1. Voltage and Frequency Change Overhead

The frequency change for modern processors takes around tens of microseconds depending on the amount and (up or down) direction of the frequency change. According to (park2013accurate, ), the frequency downscaling for Intel Core2 Duo E6850 processor takes approximately between 10 to 60 microseconds depending on the amount of the frequency change. In contrast, the transition to and from sleep modes of modern processors usually takes in the order of a few milliseconds. Therefore, for our modeling, we ignore the latency overhead of switching frequencies compared to that of transition to and from sleep modes of a processor. The energy overhead associated with frequency change is also small and neglected in our modeling.

2.2. Task Model

Tasks to be scheduled are modeled as a task graph which itself is a directed acyclic graph (DAG) represented by $G(V,E,T_{d})$, in which $V$ denotes the set of tasks (we have a total of $n$ tasks), $E$ denotes data dependencies among tasks, and $T_{d}$ denotes the period of the task graph (i.e., tasks in the task graph are repeated after $T_{d}$). Each task graph should be scheduled before the arrival of the next one (i.e., $T_{d}$ acts as a hard deadline for scheduling of tasks). In this paper, the workload of each task is represented by the total number of processor cycles required to perform that task completely. For task $u$ ($u=1,2,...,n$), this workload is represented by $W_{u}$.

2.3. Energy Model

For modeling the processor power consumption during executing a task with frequency $f$, similar to (gerards2015interplay, ), the following model would be exploited:

[TABLE]

in which $af^{\alpha}$ represents dynamic power portion, and $bf+c$ represents static power portion of total processor power consumption. $\alpha$ indicates the technology-dependent dynamic power exponent; usually $\approx$ 3. $a$ is a constant that depends on the average switched capacitance and the average activity factor. Therefore, energy consumption in one clock cycle, when executing a task with frequency $f$, is obtained via the following formulation:

[TABLE]

For modeling the processor energy consumption during an idle time, $E_{idle}$ function is used according to the formulation presented in (3). Here, for the illustration purposes, we only use one sleep mode for switching to and waking up from, and power consumption during this sleep mode is considered to be zero (It is straightforward to extend the work to support multiple sleep modes each associated with a different non-zero power consumption):

[TABLE]

where $I$ represents the idle time, $c$ is the frequency-independent component of power consumption (by setting $f$ to zero in (1)), and $E_{sw}$ is the switching energy overhead for both switching to the sleep mode and waking up from it. $T_{be}$ represents break-even time and is obtained as follows:

[TABLE]

where $\frac{E_{sw}}{c}$ represents the minimum amount the idle time should be so that switching to the sleep mode and waking up from it causes energy savings, and $T_{sw}$ is the physical time needed for both switching to the sleep mode and waking up from it. $T_{be}$ is the maximum of these two values. Furthermore, the third term in (3) conveys the fact that if no task is assigned to a processor or equivalently $I=T_{d}$, that processor is not used for scheduling of tasks and thus does not contribute to the total energy consumption at all. Therefore, our model explores the possibility of scheduling the task graph on a subset of $K$ available processors if it results in energy savings.

2.4. Problem Statement

Using the combination of DVFS and DPM, where each of these techniques can be done for each processor independently, we are looking for energy-optimized scheduling of the task graph represented by $G(V,E,T_{d})$ on a platform comprising of $K$ homogeneous processors subject to a hard deadline. Each processor supports a set of $m$ distinct frequencies: $\{f_{1},f_{2},...,f_{m}\}$. We are considering a non-preemptive scheduling method. Therefore, when the execution of a task starts on each of the processors, it continues until the task completion without any interruption. Consequently, for each task, we are looking for optimum values for: processor assignment for the task, task execution start time, and distribution of the total number of required processor cycles for the complete execution of the task among $m$ available frequencies.

3. Proposed Method

3.1. Constraints of the Proposed Scheduling Model

In this section, we formulate constraints of the proposed scheduling model. Duration of task $u$ ($u=1,2,...,n$) is formulated as follows:

[TABLE]

where $N_{u,i}$ indicates number of processor cycles performed at $f_{i}$ ($i=1,2,...,m$) for the execution of task $u$. Therefore:

[TABLE]

According to (2) and (5), energy consumption during the execution of task $u$ can be formulated as follows:

[TABLE]

To ensure each task finishes its execution before $T_{d}$, for $u=1,2,...,n,$ we have:

[TABLE]

where $S_{u}$ represents start time of the execution of task $u$. Furthermore, the precedence constraint is formulated as follows:

[TABLE]

Here, we do not consider any inter-task communication cost associated with $e(u,v)$ for sending output data of task $u$ to input data of task $v$ (The model can be easily extended to incorporate this cost).

For processor assignment for task $u$ to processor $k,k=1,2,...,K,$ we introduce the decision variable of $P_{k,u}$ which is defined as follows:

[TABLE]

Therefore, we have the following constraint:

[TABLE]

One other important constraint that needs to be satisfied is that the execution of tasks assigned to the same processor shall not overlap each other (non-preemptive scheduling). For this, we define an auxiliary decision variable called $O_{k,u,v}$ representing ordering of tasks. For $k=1,2,...,K$; $u=1,2,...,n$; $v=1,2,...,n,v\neq u;$ we define:

[TABLE]

In addition, if task $v$ is the first task assigned to processor $k$, we define $O_{k,0,v}$ to be 1 (and is 0 otherwise). On the other hand, if task $u$ is the last task assigned to processor $k$, we define $O_{k,u,n+1}$ to be 1 (and is 0 otherwise). Furthermore, if there is no task assigned to processor $k$, we define $O_{k,0,n+1}$ to be 1 (and is 0 otherwise). Accordingly, using (12) and the definitions provided for $O_{k,0,v}$, $O_{k,u,n+1}$ and $O_{k,0,n+1}$, we have the following constraints for $k=1,2,...,K$:

[TABLE]

[TABLE]

According to (13), if task $u$ is assigned to processor $k$ ($P_{k,u}=1$), either there is one and only one task scheduled immediately after task $u$ on processor $k$ or task u is the last task assigned to processor $k$. Similarly, according to (14), if task $v$ is assigned to processor $k$ ($P_{k,v}=1$), either there is one and only one task scheduled immediately before task $v$ on processor $k$ or task $v$ is the first task assigned to processor $k$. In both (13) and (14), $P_{k,0}$ and $P_{k,n+1}$ are defined as 1 for all $k=1,2,...,K$.

For non-preemptive scheduling we should have:

[TABLE]

which can be formulated as the following linear constraint:

[TABLE]

3.2. Modeling Idle Intervals

Using $O_{k,u,v}$ variables introduced in Section 3.1, we can conveniently model idle intervals in an MPSoC platform. Specifically, for each task $v$ ($v=1,2,...,n$), we formulate the amount of the idle time before servicing task $v$ on the processor to which task $v$ is assigned. When task $v$ is not the first task scheduled on the processor to which it is assigned, the idle time before servicing task $v$ can be written as follows:

[TABLE]

If task $v$ is the first task scheduled on any of $K$ processors, the first term in multiplication in (3.2) causes $I_{v}$ to be zero. In that case, idle time before servicing task $v$ on the processor $k$ to which the task is assigned is obtained using the following:

[TABLE]

In (3.2), the second term in summation represents the idle time on processor $k$ before servicing its first assigned task in the current period. On the other hand, The first term in the summation in (3.2) represents the idle time on that processor after servicing its last assigned task in the previous period. This interval should also be taken into account when calculating the amount of idle time before servicing first task scheduled on processor $k$. If there is no task assigned to processor $k$ at all, (3.2) would give the value of $T_{d}$ for $I^{\prime}_{k}$.

3.3. Objective Function

Subject to constraints formulated so far, we are trying to minimize the following objective function which represents the total energy consumption:

[TABLE]

The objective function of (19), alongside the formulated constraints, forms a mixed integer programming over the positive real variables of $S_{u}$ and $N_{u,i}$; and the Boolean decision variables of $P_{k,u}$ and $O_{k,u,v}$. The number of these variables in our problem are $n$, $nm$, $nk$, and $(n+1)^{2}k-nk$, respectively.

However, due to formulations presented for idle time intervals in (3.2) and (3.2), and the concave piece-wise behavior of $E_{idle}$ function in (3) in a minimization problem, it is a non-linear non-convex programming ($E_{task(u)}$ in (19) is linear with respect to positive real variables of $N_{u,i}$ and this term does not contribute to the nonlinearity of the problem).

For linearizing (3.2) and (3.2), we use the lemma mentioned in (chen2014energy, ), where this lemma is stated as follows: Given constants $s_{1}$ and $s_{2}$, if $P_{1}$ and $P_{2}$ are two constraint spaces where $P_{1}$ is $\{[t,b,x]\,|\,t=bx,\,-s1\leq x\leq s2,\,b\in\{0,1\}\}$, and $P_{2}$ is $\{[t,b,x]\,|\,-bs_{1}\leq t\leq bs_{2},\,t+bs_{1}-x-s_{1}\leq 0,\,t-bs_{2}-x+s_{2}\geq 0,\,b\in\{0,1\}\}$, then, $P_{1}$ and $P_{2}$ are equivalent. Proof of this lemma is given in (chen2014energy, ). With this lemma, we can substitute multiplication of a Boolean decision variable and a bounded real variable, with a newly introduced bounded real variable and three added linear constraints indicated in $P2$). Using this lemma multiple times, we can reach linear representations for idle time interval formulations in (3.2) and (3.2) at the end.

Furthermore, $E_{idle}(I_{v})$ in (19) can be written as follows:

[TABLE]

where $S_{v}$ is a Boolean decision variable which is 1 when $T_{be}\leq I_{v}<T_{d}$ and is 0 otherwise ($I<T_{be}$). Therefore, this decision variable represents switching and whether we put the processor during $I_{v}$ in the sleep mode or not. Since $I_{v}$ represents the amount of idle time before servicing task $v$ on the processor to which task $v$ is assigned when task $v$ is not the first task on that processor, $I_{v}$ can never be $T_{d}$. Therefore, we do not need to formulate the third term of (3) in (20). Corresponding constraint for $S_{v}$ ($v=1,2,...,n$), is written as follows:

[TABLE]

For $E_{idle}(I^{\prime}_{k})$, a similar formulation like (20) can be used except that we need another Boolean decision variable called $U_{k}$ which represents whether we assign any task to processor $k$ or not. When $U_{k}$ is 0, it means processor $k$ is not used at all for scheduling the task graph and thus does not contribute to the energy consumption in (19). Therefore, $U_{k}$ is 1 when we assign one or more tasks to processor $k$ ($I^{\prime}_{k}<T_{d}$) and is 0 otherwise ($I^{\prime}_{k}=T_{d}$, or equivalently: $T_{d}\leq I^{\prime}_{k}\leq T_{d}$). Accordingly, $E_{idle}(I^{\prime}_{k})$ in (19) can be written as follows:

[TABLE]

where $S^{\prime}_{k}$ represents whether we switch the processor during $I^{\prime}_{k}$ to the sleep mode or not (similar to $S_{v}$). The usage of $U_{k}$ in (22) allows formulating the third term of (3). Corresponding constraints for $S^{\prime}_{k}$ and $U_{k}$ ($k=1,2,...,K$) are written as follows:

[TABLE]

[TABLE]

In order to linearize (20) and (22), we again use the aforementioned lemma. However, for (22), where we have a multiplication of two Boolean decision variables, we also need the following lemma: If $P_{1}$ and $P_{2}$ are two constraint spaces where $P_{1}$ is $\{[z,x,y]\,|\,z=xy,\,x\in\{0,1\},\,y\in\{0,1\}\}$, and $P_{2}$ is $\{[z,x,y]\,|\,z\leq x,\,z\leq y,\,x+y-z\leq 1,\,x\in\{0,1\},\,y\in\{0,1\}\}$, then, $P_{1}$ and $P_{2}$ are equivalent. Using these lemmas and methods for linearizing the objective function of (19), the energy-optimized scheduling problem expressed in Section 2.4 is modeled as an MILP formulation.

4. Results

4.1. Experiment Setup

In order to solve the formulated MILP, we use IBM ILOG CPLEX Optimization Studio (cplex, ). The platform on which simulations are performed is a computer with a 3.2 GHz Intel Core i7-8700 Processor and 16 GB RAM. Using (chen2014energy, ) for obtaining energy model parameters, the frequency-independent component of processor power consumption, which is represented by $c$ in (1), is obtained as $276\,mW$. Each processor can operate independently of other processors at either $f_{1}=1.01\,GHz$, $f_{2}=1.26\,GHz$, $f_{3}=1.53\,GHz$, $f_{4}=1.81\,GHz$, $f_{5}=2.1\,GHz$. For these frequencies, frequency-dependent component of processor power consumption, which is represented by $af^{\alpha}+bf$ in (1), is $430.9\,mW$, $556.8\,mW$, $710.7\,mW$, $896.5\,mW$, and $1118.2\,mW$, respectively. Using curve fitting, we obtain $a=23.8729$, $b=401.6654$, and $\alpha=3.2941$ in (1). $E_{sw}$ and $T_{sw}$ are set as $385\,\mu J$ and $5\,ms$. Here, We consider a architecture with 4 processors. Simulations are performed on 8 task graphs randomly generated using TGFF (dick1998tgff, ), which is a randomized task graph generator widely used in the literature to evaluate the performance of scheduling algorithms. Detailed information for each task graph is presented in Table 1. For studied task graphs, the average workload of each task is set to $2\times 10^{6}$ cycles (around $1\,ms$ execution time under maximum frequency). The maximum in-degree and out-degree for each node is set to 2 and 3, respectively. The number of tasks in studied random task graphs ranges from 7 to 28.

To evaluate the advantage of our modeling of idle intervals in multiprocessor systems, we consider two cases:

1. A baseline case which uses only the first term of (19) as the objective function alongside with constraints of (5) to (14), and (16). In other words, in this baseline case, we do not use any idle time-related terms in the objective function or constraints. 2) Using (19) as the objective function alongside all constraints and linearization techniques mentioned in Section 3 (this case is our proposed method). In the baseline case, switching to the sleep mode during an idle time is done, if possible, after the scheduling is finished (i.e., DPM is not integrated with DVFS and scheduling in the baseline case). Therefore, the baseline case is an integrated Scheduling and Clock-and-voltage scaling followed by mode Transition algorithm (iSC+T). The second case, which is our proposed method, is referred to as an integrated Scheduling, Clock-and-voltage scaling, and mode Transition algorithm (iSCT).

4.2. Effect of Modeling Idle Intervals

According to Table 1, including the energy consumption of modeled idle intervals in the objective function causes an average energy saving of 15.34% (up to 25.21%) for iSCT versus iSC+T. To better observe the contribution of modeling idle intervals in an MPSoC platform, for each scheduled task graph, the total number of idle intervals on all processors, and total time of these idle intervals are shown in Table 2 for both iSCT and iSC+T. Furthermore, for each scheduled task graph, the number of used processors for the scheduling of that task graph, out of maximum 4 processors, is also presented in Table 2 for both iSCT and iSC+T.

According to Table 2, while for all scheduled task graphs, the total time of idle intervals are higher or the same for iSCT compared to iSC+T, the number of idle intervals for iSCT are notably fewer than the number of idle intervals for iSC+T (on average fewer than half). Therefore, by including the energy consumption of modeled idle intervals in the objective function of (19), instead of having a number of distributed short idle intervals, we will have fewer merged longer idle intervals. This results in more opportunities for switching the processors to the sleep mode during idle intervals and thus more energy savings (as indicated in Table 1). In fact, for task graphs studied in this paper, the percentage of idle intervals that are longer than $T_{be}$, and thus we can switch the processor to the sleep mode, are 91.67 % and 32.31 % for iSCT and iSC+T, respectively.

On the other hand, as indicated in Table 2, iSCT explores the possibility of the usage of a subset of 4 processors if it results in energy savings. For discussed task graphs in this paper, iSCT always uses fewer than 4 processors for the scheduling. The unused processors do not contribute to the energy consumption at all (we do not need to switch them to the sleep mode and wake them up in every time period). This can be helpful in terms of energy efficiency, particularly when the energy overhead of switching processors is relatively high. Reference (chen2014energy, ) cannot take advantage of this since the processor assignment for tasks to be scheduled is assumed to be known in advance and it is not integrated in their MILP formulation.

On the platform we performed simulations, iSCT and iSC+T approaches on average generated results for studied task graphs in less than 69 and 1 minutes, respectively. Since we are considering scheduling of a periodic task graph, these simulations are done offline only once for one period of the task graph. The obtained scheduling can be programmed to a MPSoC for real-time scheduling of each arriving period of the task graph.

4.3. A Heuristic Approach to Solve the Model

Here, we propose a two-stage heuristic algorithm to solve the formulated model: 1) We first determine and fix the values of $O_{k,u,v}$ and $P_{k,u}$ variables using a polynomial-time list scheduling algorithm. 2) Using fixed $O_{k,u,v}$ and $P_{k,u}$ values, the number of variables in the original MILP problem reduces significantly. Also, (3.2) and (3.2) will become linear formulations in the first place, and we do not anymore need to use the first lemma presented in Section 3.3 multiple times to linearize them. This further reduces the number of variables of the MILP problem considerably (since each time using of this lemma adds one set of real variables, plus three sets of constraints). Then, the new formulated problem with considerably fewer number of variables, which is still an MILP due to the usage of (20) and (22) in the objective function of (19), will be solved to obtain values of $S_{u}$ and $N_{u,i}$.

For the first stage, we use a variant of heterogeneous earliest finish time (HEFT) algorithm (topcuoglu2002performance, ). While this algorithm aims for heterogeneous platforms, it can be applied to a homogeneous platform similar to our paper as well. Basically, in this algorithm, tasks are ordered according to their upward rank, which is defined recursively for each task as follows:

[TABLE]

where here, $Dur^{*}_{u}$ is the duration of the task $u$ when all of its workload is executed using maximum available frequency, and $succ(u)$ is the set of immediate successors of task $u$. Ranks of the tasks are computed recursively starting from exit tasks of the task graph (exit tasks are the ones with out-degree of zero). The upward rank of exit tasks are equal to their corresponding $Dur^{*}$ values. Basically, $rank_{up}(u)$ indicates the length of critical path from task $u$ to exit tasks, including $Dur^{*}_{u}$ itself.

After the calculation of ranks for all the tasks, a task list is generated by sorting the tasks in the decreasing order of their ranks. Tie-breaking is done randomly. Then, tasks are scheduled on processors based on the order of the task list. Each task can only be scheduled after a time called ready_time of that task, which indicates the time that the execution of all immediate predecessors of that task has completed. For each task, we look for the first idle interval on each processor after the task ready_time, with the amount of at least $Dur^{*}$ of that task, and assign the task to the processor which gives us the earliest finish time. Since the task list sorted by the decreasing order of ranks gives a topological sorting of the DAG (topcuoglu2002performance, ), when we choose a task for scheduling, its predecessors have already been scheduled. The time complexity of HEFT algorithm is $O(|E|\times K)$ where $|E|$ denotes the number of edges of the DAG and $K$ denotes the number of processors (topcuoglu2002performance, ).

Using HEFT in the first stage of our heuristic approach, we determine the processor assignment for each task ($P_{k,u}$), and ordering of tasks on each processor ($O_{k,u,v}$). Note that obtained start times for tasks after the first stage just show relative ordering of tasks on each processor. Also, we only used maximum frequency in the first stage. Next, in the second stage, we solve the newly derived MILP, which has been obtained after fixing $O_{k,u,v}$ and $P_{k,u}$ values in the first stage, and has considerably fewer number of variables compared to the original MILP. This gives us the values for $S_{u}$ and $N_{u,i}$ variables. On average, on the platform we performed simulations, solving the newly derived MILP provided results for studied task graphs in less than 2 seconds, which is considerably less than the simulation time of solving the original MILP.

Fig. 1 shows a comparison between the energy consumption obtained from iSCT, and the energy consumption obtained from solving the problem using the proposed heuristic approach. According to Fig. 1, the heuristic method provides close estimates compared to the optimum solution. The values of energy consumption obtained from the heuristic approach are on average 5.66% higher than the optimum solution.

5. Conclusions and Future Work

In this paper, by proposing a method for modeling idle intervals in multiprocessor systems, we presented an energy optimization MILP formulation integrating both DVFS and DPM with scheduling of real-time tasks with precedence and time constraints. By solving the MILP, for each task, we obtain the optimum processor assignment, execution start time, and the distribution of its workload among available frequencies of the processor. Results show the effectiveness of our modeling of idle intervals in MPSoCs in terms of energy efficiency. We also presented a heuristic approach for solving the MILP which provided close results compared to optimum results. It is worth mentioning that although our proposed model focuses on MPSoCs, it can also be applicable to servers in data centers by using proper energy model parameters of those platforms.

For future work, workload of tasks can be investigated to represent more than just the processor cycle count; e.g., the memory requirement, or the possibility of executing the entire or part of a task on GPUs can be modeled and investigated. Also, obtaining a variant of the proposed model for heterogeneous processors could be another potential future direction.