# Rapid Cycle-Accurate Simulator for High-Level Synthesis

## TL;DR

This paper introduces FLASH, a rapid, cycle-accurate HLS simulation flow that bridges the semantic gap, ensures correctness, and is three orders of magnitude faster than RTL simulation.

## Contribution

FLASH automatically constructs cycle-accurate models from HLS scheduling info, improving speed and correctness over existing FPGA simulators.

## Key findings

- FLASH runs 1000x faster than RTL simulation.
- It maintains C semantics in cycle-accurate simulation.
- The approach effectively bridges the semantic gap in HLS simulation.

## Abstract

A large semantic gap between the high-level synthesis (HLS) design and the low-level (on-board or RTL) simulation environment often creates a barrier for those who are not FPGA experts. Moreover, such low-level simulation takes a long time to complete. Software-based HLS simulators can help bridge this gap and accelerate the simulation process; however, we found that the current FPGA HLS commercial software simulators sometimes produce incorrect results. In order to solve this correctness issue while maintaining the high speed of a software-based simulator, this paper proposes a new HLS simulation flow named FLASH. The main idea behind the proposed flow is to extract the scheduling information from the HLS tool and automatically construct an equivalent cycle-accurate simulation model while preserving C semantics. Experimental results show that FLASH runs three orders of magnitude faster than the RTL simulation.