Design of an Efficient Single-Stage and 2-Stages Class-E Power Amplifier (2.4GHz) for Internet-of-Things

TL;DR

This paper presents the design and testing of efficient single-stage and 2-stage Class-E power amplifiers at 2.4 GHz for IoT, achieving high gain and efficiency through harmonic suppression and impedance matching.

Contribution

It introduces a novel harmonic suppression technique and optimized impedance matching for 2.4 GHz Class-E PAs, with both simulation and experimental validation.

Findings

Single-stage PA gain: 17.58dB (simulated), 16.7dB (experimental)

2-stage PA gain: 34.6dB (simulated), 30.5dB (experimental)

Efficiency up to 55% in simulation and over 49% experimentally

Abstract

In this work, the designs of a single-stage and 2-stage 2.4 GHz power amplifier (PA) are presented. The proposed PAs have been designed to provide high gain and improved efficiency using harmonic suppression and optimized impedance matching techniques. There are two harmonic suppression circuits, each stage of the PA consists of 2 capacitors and 2 inductors, which will help to suppress the harmonic frequency for 2.4 GHz. These suppression circuits will help to enhance the overall efficiency of the PAs. Both the PAs are provided with a VCC supply of 4.2V. Input and output impedances are matched to 50 ohms. Simulation and experimental results are presented, where the simulated gain and power added efficiency (PAE) for single stage PA are 17:58dB and 53%, respectively. While the experimental gain and PAE are 16:7dB and 49.5%, respectively. On the other hand, for 2-stages PA, simulated gain comes out to be 34.6dB and PAE is 55%, while the experimental gain and PAE are 30.5dB and 53.1%, respectively. The final design is being fabricated on the Taconic printed circuit board (PCB) with a thickness of 0.79mm and the dielectric constant value of 3.2 and its dimensions are 4.6cm x 3.4cm for single stage and 5.9cm x 3.6cm for 2-stages PA.