A high-level operational semantics for hardware weak memory models
Robert J. Colvin, Graeme Smith

TL;DR
This paper introduces a high-level operational semantics for weak memory models in hardware, enabling reasoning about instruction reordering and correctness at an abstract level, validated through model checking and litmus tests.
Contribution
It presents a novel operational semantics framework for weak memory models, incorporating a wide-spectrum language and refinement laws, with implementation in Maude for validation.
Findings
Semantics accurately models TSO, ARM, and POWER architectures.
Validation against litmus tests shows high fidelity with hardware behaviors.
Framework supports reasoning about complex instruction reordering and data structure correctness.
Abstract
Modern processors deploy a variety of weak memory models, which for efficiency reasons may execute instructions in an order different to that specified by the program text. The consequences of instruction reordering can be complex and subtle, and can impact on ensuring correctness. In this paper we build on extensive work elucidating the semantics of assembler-level languages on hardware architectures with weak memory models (specifically TSO, ARM and POWER) and lift the principles to a straightforward operational semantics which allows reasoning at a higher level of abstraction. To this end we introduce a wide-spectrum language that encompasses operations on abstract data types as well as low-level assembler code, define its operational semantics using a novel approach to allowing reordering of instructions, and derive some refinement laws that can be used to explain behaviours of real…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Distributed systems and fault tolerance · Security and Verification in Computing
