Architectural exploration of heterogeneous memory systems

TL;DR

This paper explores the design space of heterogeneous memory systems using a linear programming model to compare different memory technologies like SRAM and STT-RAM, aiming to optimize performance and energy efficiency.

Contribution

It introduces a linear programming-based approach for evaluating various on-chip memory technologies, facilitating their integration into production compilers.

Findings

The model effectively compares performance of different memory technologies.

Experimental results validate the model's viability for compiler integration.

Heterogeneous memory systems can be optimized using this approach.

Abstract

Heterogeneous systems appear as a viable design alternative for the dark silicon era. In this paradigm, a processor chip includes several different technological alternatives for implementing a certain logical block (e.g., core, on-chip memories) which cannot be used at the same time due to power constraints. The programmer and compiler are then responsible for selecting which of the alternatives should be used for maximizing performance and/or energy efficiency for a given application. This paper presents an initial approach for the exploration of different technological alternatives for the implementation of on-chip memories. It hinges on a linear programming-based model for theoretically comparing the performance offered by the available alternatives, namely SRAM and STT-RAM scratchpads or caches. Experimental results using a cycle-accurate simulation tool confirm that this is a viable model for implementation into production compilers.