SOT-MRAM 300mm integration for low power and ultrafast embedded memories
K. Garello, F. Yasin, S. Couet, L. Souriau, J. Swerts, S. Rao, S. Van, Beek, W. Kim, E. Liu, S. Kundu, D. Tsvetanova, N. Jossart, K. Croes, E., Grimaldi, M. Baumgartner, D. Crotti, A. Furn\'emont, P. Gambardella, G.S. Kar

TL;DR
This paper reports the first full-scale integration of SOT-MRAM on 300mm wafers using CMOS-compatible processes, achieving ultrafast switching, high endurance, and low power consumption for embedded memory applications.
Contribution
It introduces a CMOS-compatible process for integrating top-pinned perpendicular MTJ on 300mm wafers, demonstrating high-performance SOT-MRAM devices.
Findings
Endurance > 5x10^10 cycles
Switching time of 210 ps
Power consumption as low as 300 pJ
Abstract
We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a W-based SOT underlayer have very large endurance (> 5x10^10), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.
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